Analyzing RV32/RV64 Trade-offs for FreeRTOS Latency on 8-Stage RISC-V Soft Processors
This study addresses the lack of systematic guidance for implementing preemptive real-time operating systems (RTOS) on custom bare-metal RISC-V soft cores, particularly regarding the interplay among processor microarchitecture, interrupt handling, and context switching. The authors deploy FreeRTOS on an 8-stage pipelined RV32/RV64 soft core featuring machine-mode CSRs, a CLINT timer, and exception control logic, and—within a unified microarchitectural and firmware framework—employ Rhealstone-derived microbenchmarks to comparatively evaluate task-switching and preemption latencies between RV32 and RV64. Results reveal that RV64 incurs 36.6% and 17.7% higher cycle delays due to its doubled trap frame size, 64-bit pointers, and scheduler overhead. The complete RTL, firmware, and benchmark suite are open-sourced, establishing a reproducible baseline for RISC-V real-time system design.