Problem
Research questions and friction points this paper is trying to address.
RISC-V
FreeRTOS
real-time operating system
context switching
latency
Analyzing RV32/RV64 Trade-offs for FreeRTOS Latency on 8-Stage RISC-V Soft Processors
🤖 AI Summary
This study addresses the lack of systematic guidance for implementing preemptive real-time operating systems (RTOS) on custom bare-metal RISC-V soft cores, particularly regarding the interplay among processor microarchitecture, interrupt handling, and context switching. The authors deploy FreeRTOS on an 8-stage pipelined RV32/RV64 soft core featuring machine-mode CSRs, a CLINT timer, and exception control logic, and—within a unified microarchitectural and firmware framework—employ Rhealstone-derived microbenchmarks to comparatively evaluate task-switching and preemption latencies between RV32 and RV64. Results reveal that RV64 incurs 36.6% and 17.7% higher cycle delays due to its doubled trap frame size, 64-bit pointers, and scheduler overhead. The complete RTL, firmware, and benchmark suite are open-sourced, establishing a reproducible baseline for RISC-V real-time system design.
📝 Abstract
Although many commercial RISC-V platforms provide real-time operating system support, practical examples that explain how to enable a preemptive RTOS on a custom bare-metal RISC-V soft processor remain limited, leaving the interaction between processor microarchitecture, interrupt handling, and RTOS context switching difficult to understand from simple hardware implementation examples. This paper presents the design and evaluation of FreeRTOS on custom 8-stage RV32/RV64 RISC-V soft processors with machine-mode CSRs, a CLINT timer, trap and exception control logic, and the required context-switch path. Using this platform, we compare RV32 and RV64 under the same microarchitectural organization and firmware structure using two Rhealstone-derived latency microbenchmarks, task switching and task preemption, measured with the mcycle counter. RV64 requires 36.6% and 17.7% more cycles for task switching and preemption, respectively. Instruction-level analysis attributes this overhead to the doubled RV64 trap frame, wider pointer-based kernel data structures, and 64-bit scheduler priority handling. The RTL, firmware, and benchmark code are released as open source.
Innovation
Methods, ideas, or system contributions that make the work stand out.
RISC-V soft processor
FreeRTOS latency
RV32 vs RV64
context switching overhead
real-time operating system
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