🤖 AI Summary
This study addresses the lack of systematic empirical analysis on the multidimensional design trade-offs among instruction set extensions, datapath width, and pipeline depth in RISC-V microarchitectures under a unified baseline. Building upon a common five-stage pipeline, the authors implement ten incrementally evolved FPGA prototypes, co-varying RV32/RV64 datapaths, I/IM instruction sets, and pipeline depths from five to eight stages. An iterative timing-convergence methodology combined with Dhrystone and CoreMark benchmarks enables controlled evaluation. The work reveals, for the first time under such conditions, that frequency gains do not translate linearly into throughput improvements, that RV32 consistently outperforms RV64 in both absolute performance and resource efficiency, and that an eight-stage pipeline markedly reduces resource utilization. Notably, RV32IM achieves a frequency increase from 43 MHz to 126 MHz, yielding 64% higher Dhrystone throughput and a 300% improvement in CoreMark. All RTL and configuration files are publicly released.
📝 Abstract
While functional RISC-V implementations are readily available in academia, controlled empirical studies that extend a single baseline architecture along multiple design axes and quantify the resulting trade-offs at each step remain scarce. This paper presents RV-IM100, a family of 10 incremental FPGA-implemented microarchitectures derived from a common 5-stage pipeline baseline, systematically varying datapath width from RV32 to RV64, instruction set from I to IM, and pipeline depth from 5 to 8~stages under controlled conditions. Using an iterative timing-closure methodology, RV32IM frequency improved from 43 to 126MHz, increasing Dhrystone throughput by 64% and CoreMark by 300%, while per-MHz efficiency decreased by 36--41%. The 6-to-7-stage transition caused throughput regression in RV64 despite higher frequency, revealing that the outcome depends on available frequency headroom. Cross-width comparison showed RV32 outperforming RV64 in absolute throughput, with per-MHz efficiency diverging by benchmark: RV64 led by 2.3% in DMIPS/MHz while RV32 led by 4.6% in CoreMark/MHz. At 8 stages, RV32 required 59% fewer LUTs, 51% fewer FFs, and 80% fewer DSPs, indicating that the resource cost of width extension substantially exceeds the modest efficiency differences. These results provide a quantitative reference for design-space exploration in RISC-V microarchitectures. All RTL sources and benchmark configurations are publicly available.