physics-informed device modeling

Traditional SPICE simulation struggles with strongly nonlinear emerging devices (e.g., ferroelectric memory) due to its reliance on time-discretized numerical solvers, inability to analytically compute derivatives, and lack of native support for inverse problems. To address these limitations, we propose NeuroSPICE—the first systematic framework integrating physics-informed neural networks (PINNs) into circuit simulation. NeuroSPICE directly solves differential-algebraic equations (DAEs) in the time domain via residual minimization and automatic differentiation, enabling end-to-end waveform prediction and generating compact, high-fidelity, differentiable analytical surrogate models. Its core innovations include breaking from conventional SPICE paradigms to natively support joint device-circuit modeling, parameter inversion, and real-time design optimization. Experiments demonstrate that NeuroSPICE significantly improves both simulation efficiency and interpretability for nonlinear circuits, establishing a new paradigm for next-generation EDA tools.

Addressing the challenge of accurately characterizing and dynamically monitoring the internal state of spintronic domain-wall memristors (SDCs), this paper proposes a physics-informed, general-purpose modeling and noise-robust estimation framework. First, we establish the first physically consistent and interpretable state evolution model for SDC memristors, grounded in fundamental spintronic mechanisms. Second, we design a noise-aware minimum-variance state estimator that directly reconstructs the internal state from time-varying voltage–current measurements—overcoming the limitations of conventional static I–V curve fitting. The framework enables reproducible, quantitative, and real-time state characterization. Experimental validation demonstrates a 42% reduction in state estimation error compared to standard approaches, significantly enhancing monitoring reliability. This work provides a foundational tool for online state awareness and reliability assessment in neuromorphic hardware systems.

Existing memristor models for event-driven neuromorphic systems—such as spiking neural networks—suffer from discretization-induced timing errors and poor generalizability due to reliance on fixed-time-step numerical simulation. Method: This paper introduces the first general-purpose, event-driven memristor modeling framework. It unifies volatile state variables to capture diverse failure mechanisms; reformulates the generalized metastable switch (MSS) model in event-driven form; and integrates physics-informed filament growth dynamics with a linear conductance drift model, calibrated using experimentally measured drift data from titanium oxide devices. Contribution/Results: The framework eliminates temporal discretization error, enabling high-fidelity, low-overhead stochastic behavior simulation. It supports large-scale, brain-inspired hardware–software co-simulation, significantly improving model portability across platforms and enhancing physical interpretability through mechanistic fidelity.

High energy consumption in resistive switching of first-order memristors hinders their deployment in energy-efficient neuromorphic hardware. Method: We propose a general optimal control framework to minimize programming energy under constraints on voltage amplitude and switching time. By formulating a differential-algebraic equation system based on the TEAM model and dynamic equilibrium, we analytically derive energy-efficiency bounds for voltage-driven waveforms using variational calculus and numerical optimization. Contribution/Results: Theoretical analysis and simulations demonstrate that, across broad parameter ranges, globally optimal control is achieved by either a single rectangular pulse or a polarity-specific piecewise-constant pulse—bypassing the conventional “voltage–time trade-off.” This work provides the first rigorous control-theoretic proof of the structural optimality of low-power memristor programming. It yields implementable programming protocols and design principles for high-density, ultra-low-power neuromorphic systems.

To address the low energy efficiency and high latency of data-intensive intelligent algorithms arising from the memory–computation separation inherent in von Neumann architectures, this project proposes a novel in-memory computing paradigm based on spintronics. We systematically survey and experimentally validate five physically distinct spintronic memristive devices—magnetic tunnel junctions (MTJs), ensembles of nanomagnets, domain walls, topological structures (e.g., skyrmions), and spin waves—and uncover their diverse dynamical behaviors (steady-state, oscillatory, stochastic, and chaotic) as enabling mechanisms for neuromorphic computing, spiking neural networks, stochastic sampling, and chaotic signal generation. The work establishes device-level foundations for high-energy-efficiency, high-density intelligent hardware and demonstrates programmable in-memory logic implementation.

This work addresses the reliability challenges—such as read/write errors and soft errors—that hinder the deployment of nanoscale memristive devices, including ReRAM and STT-RAM, in high-density, low-power memory and in-memory computing applications. The study systematically investigates the underlying reliability mechanisms of these two device types and, for the first time, uncovers the coupling effects among multiple reliability parameters, elucidating both their detrimental and beneficial impacts. Building on these insights, the authors propose an application-oriented, holistic fault-tolerance strategy that integrates circuit-level and architecture-level techniques within a crossbar array framework. This approach not only enhances device reliability but also extends the capability of memristor-based systems to perform logic and arithmetic operations in compute-in-memory architectures, thereby offering a robust theoretical foundation and practical pathway for reliable deployment of memristors in emerging computing paradigms.

This work addresses the limitations of conventional one-dimensional Fokker–Planck models in accurately predicting the write error rate (WER) of MRAM devices incorporating in-plane magnetic fields, field-like torques, or asymmetric energy barriers. The authors present the first two-dimensional Fokker–Planck solver formulated on the unit sphere using a finite volume method, supporting four discretization schemes: central differencing, Scharfetter–Gummel, upwind, and a novel hybrid adaptive blending strategy. Validation against million-trajectory stochastic Landau–Lifshitz–Gilbert (sLLG) simulations demonstrates that central differencing faithfully reproduces realistic WER under strong two-dimensional effects. Furthermore, the proposed hybrid adaptive scheme achieves both high accuracy and numerical stability across a wide range of Péclet numbers, significantly enhancing the fidelity and unbiasedness of switching dynamics predictions for next-generation magnetic memory devices.

This work addresses the electromigration (EM) reliability challenges posed by high current densities in future heterogeneous integrated systems. Moving beyond the limitations of conventional rule-based approaches, it proposes a highly accurate and scalable EM analysis and optimization framework that integrates physical mechanisms with circuit-level information. By systematically comparing physics-based and empirical models, the study identifies key open issues and establishes an efficient computational pathway to enable circuit-aware, large-scale EM assessment. This research advances EM reliability design from empirical rules toward a physics-driven paradigm, laying a robust theoretical and technical foundation for industrial-grade EM reliability assurance in high-performance integrated circuits.

This work addresses the urgent need for efficient solutions to differential and matrix equations in artificial intelligence and scientific computing by transcending the energy-efficiency and speed limitations of conventional digital computation. It pioneers a unified framework that integrates both classes of equations within a modern analog computing paradigm. Leveraging hardware platforms such as analog CMOS circuits and memristor crossbar arrays, the study systematically constructs a computational primitive centered on matrix-vector multiplication, thereby uncovering intrinsic connections among differential equation solvers, matrix equation solvers, and in-memory computing. The research highlights the superior energy efficiency and parallelism offered by memristor arrays while rigorously examining critical challenges including numerical precision and scalability, ultimately establishing analog computing as a promising enabler for next-generation high-performance computing.

This work proposes a device–circuit–system co-design methodology to efficiently implement short-term plasticity (STP) in neuromorphic hardware for temporal information processing. By harnessing the nonequilibrium ion dynamics of electrochemical random-access memory (ECRAM) devices—traditionally regarded as a defect—as an intrinsic STP mechanism, the authors construct leaky integrate-and-fire (LIF) neuron circuits with delayed feedback. This architecture enables concurrent dynamic modulation of synaptic weights and neuronal excitability through transient conductance changes. A compact behavioral model, calibrated against experimental characterization, is employed in circuit- and network-level simulations, demonstrating tunable temporal filtering and frequency-selective spiking responses at an ultralow energy cost of merely 2 pJ per spike. The approach proves adaptable across diverse neuronal topologies, offering a scalable solution for energy-efficient neuromorphic computing.