cycle-level timing analysis

To address the low efficiency and difficulty in root-cause localization during pre-signoff MCMM timing debugging in VLSI design, this paper proposes a multi-LLM collaborative intelligent agent system. Methodologically, it introduces (1) the Timing Debugging Relation Graph (TDRG)—the first domain-specific knowledge graph integrating circuit topology and timing constraints; (2) an Agentic RAG framework unifying graph-based retrieval, executable code reasoning, and hierarchical planning; and (3) an end-to-end pipeline for automated report parsing, root-cause identification, and repair recommendation generation. Evaluated on industrial-scale benchmarks, the system achieves 98% success rate on single-report debugging and 90% on multi-report joint debugging, substantially reducing debug turnaround time. This work represents the first systematic adoption of embodied intelligent agents in VLSI timing verification, establishing a new paradigm for AI-driven signoff automation.

To address the prohibitively slow speed of cycle-accurate simulators (e.g., gem5) in microarchitectural design space exploration, this paper proposes Concorde—a CPU performance modeling framework that synergistically integrates component-wise analytical modeling with lightweight machine learning. Its key innovation lies in the first use of interpretable, analytically derived performance distributions—characterizing caches, pipelines, and branch predictors—as input features to drive distribution-aware representation learning and efficient regression for program-level CPI prediction. Compared to gem5, Concorde achieves >10⁵× speedup with only ~2% mean absolute CPI error. It enables 150 million design evaluations within one hour and supports fine-grained, cross-program and cross-microarchitecture performance attribution. By unifying analytical insight with data-driven generalization, Concorde overcomes the longstanding accuracy-efficiency trade-off inherent in both traditional simulation and purely empirical modeling approaches.

Accelerator Design Language (ADL) compilers suffer from unpredictable hardware performance due to the semantic gap between high-level abstractions and low-level implementations, compounded by reliance on heuristic optimizations. This work introduces Petal, the first tool enabling cycle-accurate, interpretable performance analysis for Calyx-based accelerators. Petal bridges the abstraction gap via three key techniques: source-code instrumentation, RTL-simulation trace collection, and a novel reverse-mapping algorithm that associates low-level timing events in synthesized hardware with high-level control-flow constructs. Crucially, it abandons the “compiler-perfection” assumption, instead exposing how concrete compilation decisions impact end-to-end latency. Evaluated on multiple real-world accelerator designs, Petal identifies subtle, manually elusive bottlenecks—enabling targeted manual optimizations that reduce total execution cycles by up to 46.9% for one application.

Traditional static timing analysis (STA) suffers from low computational efficiency and poor utilization of heterogeneous hardware in large-scale industrial designs. To address this, we propose HeteroSTA—the first end-to-end CPU-GPU co-execution STA engine. HeteroSTA natively supports multi-precision delay modeling, full SDC constraint parsing, and multi-clock-domain analysis. It employs GPU-accelerated graph traversal and path-based timing analysis algorithms, enabling fully GPU-accelerated end-to-end STA. A zero-overhead flattened API unifies graph-, path-, and timing-query interfaces, while dual deployment modes—shared library and standalone binary—are provided. Experimental evaluation demonstrates significant speedups over baseline tools in standalone mode, within DREAMPlace 4.0, and in timing-driven routing, achieving performance competitive with industrial-grade STA tools. The source code is publicly released to facilitate both academic research and industrial integration.

Existing hardware assertion generation methods suffer from poor scalability to industrial-scale designs, low assertion quality, insufficient functional coverage depth, and limited interpretability. Method: We introduce the first LLM evaluation benchmark for Verilog designs—comprising 100 open-source circuits and formally verified “gold-standard” assertions—and propose a dedicated evaluation framework integrating functional equivalence checking, multi-dimensional quality metrics, and context-example sensitivity analysis. Contribution/Results: This work fills a critical gap in quantitative LLM assessment for hardware verification. Experiments reveal that state-of-the-art LLMs achieve less than 35% assertion correctness overall, though performance improves markedly with increasing context examples. Systematic deficiencies are identified in modeling temporal logic and finite-state machines. Our benchmark, methodology, and empirical findings provide foundational resources and evidence for advancing LLM-driven hardware verification.

Extracting high-level message flows from complex SoC communication traces is challenging due to message interleaving and causal ambiguity, which often lead to combinatorial explosion of candidates and misinterpretation of system behavior. This work proposes an architecture-guided, two-stage hierarchical mining approach: it first extracts elementary communication patterns locally at each interface, then globally synthesizes cross-component high-level message flows by leveraging the SoC’s design architecture. By integrating local pattern discovery with global architectural constraints, the method effectively mitigates pattern explosion and ambiguity, substantially improving the accuracy of communication behavior modeling. Experimental results on both synthetic traces and realistic SoC traces generated by GEM5 demonstrate that the proposed technique significantly outperforms existing methods in message flow extraction accuracy, making it well-suited for practical SoC verification scenarios.

Existing architectural simulators struggle to uncover the complex causal relationships between microarchitectural events and program behavior, making it difficult to attribute performance bottlenecks across abstraction layers. This work proposes Microflow, an observability framework that treats causality as a first-class analytical construct. Microflow introduces MFIR, an intermediate representation that explicitly encodes software-hardware dependencies, enabling queryable causal inference, revelation of latent phenomena, and precise critical path decomposition. By integrating counterfactual analysis with cross-layer dependency modeling, Microflow successfully identifies hidden bottlenecks on SPEC CPU 2017 benchmarks that are missed by conventional approaches—such as implicit misprediction overhead in leela and inter-loop resource contention in mcf.

This work addresses the significant discrepancies between microarchitectural simulators and actual RTL implementations, which undermine the reliability of performance prediction. To this end, we propose Microarchitecture Cliffs, a benchmark generation methodology that constructs targeted test cases to enable, for the first time, precise attribution of simulator inaccuracies to individual microarchitectural features, accompanied by an automated calibration pipeline. Focusing on the XiangShan CPU and its gem5 simulation versus RTL implementation, our approach reduces the performance error of XS-GEM5 from 59.2% to 1.4% on Cliff benchmarks. It also decreases absolute errors by 15.1% and 21.0% on SPECint2017 and SPECfp2017, respectively, and cuts relative errors of key microarchitectural features by 48.03%, substantially improving both calibration efficiency and interpretability.

This work addresses the error-prone and labor-intensive process of manually translating natural language specifications into formal representations for chip design verification. It presents the first end-to-end agent framework capable of automatically converting industrial-grade DRAM standard specifications from natural language into the domain-specific language DRAMPyML, which is then seamlessly integrated into hardware verification workflows to generate SystemVerilog assertions, stimuli, and functional coverage metrics. The approach is validated on real-world DRAM specifications, supported by a newly constructed evaluation benchmark, DRAMBench, and an open-sourced dataset to advance research in automated formalization of hardware specifications.

This study systematically evaluates the reliability of four machine learning–based ranking models—NeuroScalar, SimNet, Concorde, and OneDSE—in ordering hardware configurations at the program phase level for microarchitectural design space exploration. Across structural parameter and behavioral policy scenarios, the analysis—integrating cycle-accurate simulation, Bayesian accuracy assessment, and information-theoretic methods—reveals, for the first time, that a substantial fraction (22.4%) of program windows exhibit counterintuitive rankings in structural settings, and inter-model consistency remains low (23.3%–39.9%). In behavioral policy scenarios, most models fail to surpass a featureless baseline, with the best achieving only a 2.1-percentage-point improvement. The work further establishes a theoretical upper bound on ranking accuracy when critical microarchitectural states are unobservable, demonstrating inherent limitations of instruction-stream–based approaches.