circuit description parsing

Understanding the causal roles and computational mechanisms of intermediate variables—such as syntactic attributes—in Transformer language models remains challenging. Method: We propose *circuit probing*, a hypothesis-driven methodology that reverse-engineers intermediate representations encoding specific linguistic properties and precisely identifies the parameter-level neural circuits supporting them. Our approach integrates gradient-guided discovery, targeted parameter ablation, verification via diagnostic probe training, and modular attribution analysis to enable causal intervention and algorithm-level interpretation. Contribution/Results: This work unifies hypothesis testing, circuit localization, and dynamic tracing for the first time, revealing implicit algorithmic structures within models and their training-time evolution. Experiments successfully decode symbolic arithmetic logic in specialized arithmetic models, localize subject–verb agreement and reflexive pronoun processing circuits in GPT-2, and empirically confirm their progressive emergence during training.

Existing circuit representation learning methods rely heavily on graph models tailored for simple And-Inverter Graphs (AIGs), limiting their capacity to capture complex gate-level semantics; while large language models (LLMs) excel at functional understanding, they lack native awareness of netlist structural topology. This work introduces the first netlist foundation model for integrated circuit design. We propose a novel Text-Annotated Graph (TAG) representation that unifies logical expressions and physical attributes as gate-level textual features. Furthermore, we design an RTL-to-layout co-aligned multi-task self-supervised pretraining paradigm, integrating an LLM-based text encoder with a graph Transformer to jointly optimize semantic comprehension, structural learning, and cross-stage alignment. Evaluated on four functional and physical IC design tasks—including logic optimization, timing prediction, placement, and routing—the model consistently outperforms task-specific baselines and state-of-the-art AIG encoders, demonstrating superior representational generality and cross-task transferability.

Existing circuit discovery methods for language models suffer from low efficiency or poor accuracy. This work reformulates circuit discovery as an edge-level differentiable optimization problem—the first such formulation—and introduces a gradient-driven edge pruning strategy, departing from conventional neuron- or module-level pruning paradigms. Our method integrates differentiable sparse optimization with circuit fidelity evaluation and validates fidelity via Tracr-compiled models. Experiments demonstrate: (1) 50% edge reduction on GPT-2 without fidelity loss; (2) exact recovery of ground-truth circuits in Tracr models; and (3) the first discovery of instruction-tuning and in-context learning circuits in CodeLlama-13B—achieving >99.96% sparsity while preserving full-model performance, revealing substantial mechanistic overlap between the two. Overall, this work enables high-fidelity, highly sparse, and scalable automated circuit discovery in large language models.

Existing circuit discovery methods for large language models (LLMs) suffer from high computational overhead, substantial approximation error, and reliance on non-vanishing gradients. To address these limitations, we propose Context Decomposition for Transformers (CD-T), a recursive contribution decomposition and pruning framework grounded in differentiable computation graphs—requiring neither activation patching nor gradient constraints. CD-T enables fully automated, second-scale, fine-grained circuit discovery down to individual attention heads, supports modeling at arbitrary levels of abstraction, and yields circuits with perfect fidelity (1.0) and significantly reduced size. On three benchmark tasks, CD-T achieves an average ROC AUC of 97%, operates 3–4 orders of magnitude faster than state-of-the-art methods, and reproduces circuit behavior with 80% higher accuracy than random baselines.

Existing image-to-netlist conversion methods for analog schematics suffer from limited compatibility with diverse schematic styles and insufficient coverage of analog component types. To address these limitations, this paper proposes Image2Net—the first end-to-end framework supporting multi-style, multi-type analog components. Methodologically, it integrates deep learning–driven image recognition and structural parsing, rule-guided topological inference, and semantic consistency verification. We also introduce the first open-source schematic dataset featuring diversity and balanced complexity. Innovatively, we propose Netlist Edit Distance (NED) as a precision metric for quantitative evaluation. Experimental results demonstrate that Image2Net achieves an 80.77% conversion success rate on benchmark tests—surpassing state-of-the-art methods by 34.62–45.19%. Its average NED of 0.116 outperforms existing approaches by 62.1–69.6%, confirming substantial gains in structural and semantic fidelity.

Existing methods for converting circuit schematic images into EDA-processable netlists suffer from poor generalizability across IC and PCB domains, inaccurate component recognition, ambiguous connectivity inference, and frequent misinterpretation of crossing wires. This work proposes the first fully automated parsing pipeline that integrates deep learning, connected-component labeling, OCR, and vision-language models to precisely extract components, labels, and topological connections. A dedicated crossing-wire detection module is introduced to distinguish genuine electrical junctions from mere graphical overlaps. The approach unifies processing for both IC and PCB schematics and achieves a netlist accuracy of 96.67% on real-world datasets—2.72 times higher than the current state-of-the-art—while ensuring functional equivalence through graph isomorphism verification.

Existing circuit analysis methods are fragmented and lack a unified framework to support the end-to-end pipeline from discovery and evaluation to downstream interventions, often relying on manually crafted contrastive prompts that hinder reproducibility and scalability. This work proposes the first end-to-end circuit analysis toolkit, built upon a typed, serializable circuit representation that integrates multiple discovery algorithms, declarative task mapping, diagnostic utilities, and intervention modules—including pruning, editing, and steering—to enable fully interpretable mechanistic analysis throughout the pipeline. The framework facilitates automated contrastive prompt generation, cross-task transfer, and algorithmic comparison, substantially lowering barriers to both research and practical application. The complete library, along with examples and documentation, has been open-sourced to provide the community with standardized, reusable infrastructure.

This work addresses the challenge in mechanistic interpretability that, despite progress in circuit localization, component-level functional explanations remain manual and lack standardization. To this end, we propose HyVE, a novel framework that introduces language model agents into circuit explanation tasks. HyVE iteratively performs observation, hypothesis generation, and causal verification to automatically produce both component-level interpretations and circuit-level task descriptions. We construct AgenticInterpBench, the first benchmark tailored for agent-based interpretability, and evaluate HyVE across four mainstream language model architectures, demonstrating its ability to generate high-quality explanations. Our experiments reveal that causal verification constitutes the primary performance bottleneck, and we further showcase HyVE’s practical utility through a case study on arithmetic circuits in Llama-3-8B.

This work addresses the insufficient reliability of large language models in low-level operations on SPICE netlists—a limitation often masked by high-level design reasoning. To rigorously evaluate structural fidelity at the netlist level, the authors introduce NetlistBench, the first benchmark dedicated to netlist structural reliability, comprising 24 task categories and 2,342 test cases. It employs a structure-aware, deterministic verifier to assess model performance on parameter identification, connectivity editing, hierarchical manipulation, and equivalence checking. The study innovatively decouples netlist-level reliability from high-level design tasks and introduces long-span composite editing challenges alongside multi-granularity evaluation strategies. Experiments reveal near-perfect accuracy (96%–100%) on simple edits, but substantial performance drops in device insertion (41%–83%) and equivalence judgment (49%–90%). While reasoning augmentation improves weaker models, maintaining structural consistency in long-span edits remains a critical bottleneck.

This work addresses the problem of efficiently locating sparse subgraphs within Transformer computational graphs that reproduce specific behaviors—a task known as circuit discovery. To this end, it formulates circuit discovery for the first time as a graph machine learning problem and introduces Graph Circuit Learning (GCL), a framework that integrates graph neural networks with supervised, amortized learning to enable generalization across models and tasks. The method is trained on an extended version of the InterpBench benchmark and adapted from PGExplainer. Experimental results demonstrate that the best-performing GCL configuration achieves a median edge AUROC of 0.902 across 16 held-out cases, approaching the performance of EAP-IG. Ablation studies further reveal that message passing is critical to the model’s effectiveness.