deep learning compilers

Industrial-scale recommendation and ranking models feature highly complex and continuously evolving architectures, rendering traditional optimization approaches—based on manual intervention or module-level rules—difficult to scale. This work proposes the first extensible and customizable operator-level automatic transformation framework integrated into PyTorch 2.x. By leveraging FX intermediate representation, the PT2 compiler, predefined pattern matching, and a greedy search algorithm, the framework achieves general-purpose model optimizations while strictly preserving computational semantics. Evaluated on real-world industrial recommendation models, the approach delivers up to 63% inference speedup, a 6% reduction in peak memory usage, and over 400 seconds of compilation time savings. The implementation has been open-sourced as part of PyTorch 2.x.

This study addresses performance bottlenecks in large language model (LLM) fine-tuning on multi-GPU clusters, systematically analyzing three key challenges: iteration latency, VRAM utilization inefficiency, and cross-device memory transfer overhead. We propose a synergistic optimization framework integrating distributed data parallelism, hardware-aware scheduling, dynamic quantization-aware training (QAT), low-rank adaptation (LoRA/QLoRA), and direct preference optimization (DPO). Notably, this is the first unified empirical evaluation on NVIDIA H100 GPUs quantifying the efficiency boundaries of DPO, LoRA, QLoRA, and QAT under realistic fine-tuning workloads. Experiments demonstrate up to 47% reduction in iteration time, 39% decrease in peak VRAM consumption, and 52% reduction in inter-GPU memory traffic versus baseline configurations. Our core contribution is a principled, H100-targeted performance modeling and optimization methodology for LLM fine-tuning, which rigorously characterizes the applicability conditions and complementary gains of diverse parallelization strategies and precision-compression techniques.

To address the fragmented model optimization workflows and poor cross-stack compatibility in the PyTorch ecosystem, this paper introduces the first end-to-end native AI model optimization framework. It establishes a unified abstraction for low-precision tensors—supporting FP8, quantization-aware training (QAT), post-training quantization (PTQ), and 2:4 sparsity—thereby closing the loop across pretraining, fine-tuning, quantization, and deployment. A novel tensor subclass design enables seamless backend interoperability and deep integration with major toolchains, including TorchTitan/Tune, vLLM, and Hugging Face Transformers. The framework significantly improves engineering efficiency and compression consistency. It has been successfully applied to quantized-sparse variants of Llama 3.2 (1B/3B) and LlamaGuard3-8B, demonstrating practical efficacy. The open-source implementation is publicly available on GitHub, enabling efficient, full-pipeline deployment.

Existing LLM pretraining frameworks suffer from fragmentation, poor interoperability, and high maintenance overhead, severely hindering systematic evaluation and production deployment of training methodologies. This paper introduces an open-source, PyTorch-native distributed training system designed for models ranging from 10B to 400B parameters. It proposes a novel modular 3D parallelism architecture—integrating data, tensor, and pipeline parallelism—and tightly couples Float8 quantization with SymmetricMemory hardware-software co-design. The system further incorporates elastic scaling, unified checkpointing, and a reproducible experiment platform. Evaluated on the Llama 3.1 series, it achieves 65.08% speedup on 128 GPUs (8B model), an additional 12.59% gain on 256 GPUs (70B), and a further 30% improvement on 512 GPUs (405B), significantly outperforming baseline systems. The framework delivers high performance, strong scalability, and production readiness.

Modern large-scale distributed training faces sharply diminishing returns in hardware scaling: as GPU counts reach thousands, communication overhead dominates performance bottlenecks, rendering conventional parallelism strategies—data, tensor, and pipeline parallelism—suboptimal. Method: Leveraging real-world LLM training workloads, this project establishes an empirical analytical framework spanning diverse model scales, hardware configurations, and parallelization strategies. It quantifies the nonlinear relationship between accelerator count and performance gain, precisely identifying critical inflection points across model, data, and compute scaling dimensions. Contribution/Results: We discover that low-communication “suboptimal” strategies become optimal at extreme scale; we empirically determine hardware selection criteria, cluster topology requirements, and optimal parallelism combinations for training billion-parameter models. Our findings provide actionable, deployment-ready optimization guidelines for trillion-parameter LLM training infrastructures.

This work proposes KernelPro, a closed-loop multi-agent system designed to automatically generate high-performance and energy-efficient GPU kernel code. By integrating large language models with hardware micro-benchmarking tools, KernelPro employs semantic feedback operators, a two-tier tool-calling architecture, a domain-adapted Monte Carlo Tree Search (MCTS) strategy, and direct CuTe source-code generation to jointly optimize for both performance and energy efficiency. Evaluated on KernelBench, KernelPro achieves up to a 5.30× speedup over baseline implementations. Furthermore, when applied to expert-optimized Mixture-of-Experts (MoE) kernels, it outperforms hand-tuned Triton kernels by 1.23× in performance while reducing measured energy consumption by 11.6%.

This work addresses the lack of transparent, scalable, and deeply PyTorch-integrated open-source tools for post-training large language models, which hinders research iteration and deployment efficiency. We propose a native PyTorch-based, modular post-training framework centered on the principle of “hackability,” offering composable model builders, training recipes, and a distributed training stack that support diverse fine-tuning strategies and hardware configurations. While maintaining high performance and memory efficiency, the framework significantly enhances code transparency and research flexibility. Empirical evaluations demonstrate that it matches or even surpasses mainstream tools such as Axolotl and Unsloth across multiple post-training scenarios, thereby facilitating efficient and reproducible scientific exploration.

This work addresses the challenges of efficient GPU kernel development, which are hindered by hardware complexity and a scarcity of specialized optimization expertise. Existing large language models exhibit limited performance due to insufficient high-quality training data, compiler-induced biases, and poor generalization across hardware platforms. To overcome these limitations, we propose the first application of reinforcement learning (RL) fine-tuning to state-of-the-art large models—specifically GPT-5—for generating Triton GPU kernels. We introduce a custom RL training environment and the KernelBench evaluation suite. Our approach improves single-attempt generation accuracy from 43.7% to 77.0%, outperforming TorchInductor on an additional 7% of problems. When integrated into a coding agent, it solves 97.4% of tasks in an extended KernelBench, surpasses TorchInductor in 72.9% of cases, and achieves an average speedup of 2.12×.

This work addresses the challenge of automatically generating high-performance GPU tiled kernels from high-level tensor algebra expressions, thereby alleviating the burden of manual optimization. The authors propose an end-to-end compilation framework that integrates layer-wise lowering, expression rewriting, automated schedule search, reduction fusion, and tiling optimizations. For the first time, this framework automatically discovers high-efficiency kernels—comparable to FlashAttention-3—from the mathematical specification of attention operators, while introducing a novel scheduler that preserves program structural regularity. Evaluated on GH200 and RTX 5090 GPUs, the generated kernels achieve up to 23% and 42% higher throughput, respectively, and match or surpass hand-optimized cuDNN kernels across multiple long-sequence configurations.

This study addresses the inequities in AI accessibility arising from imbalanced computational resource allocation, high energy consumption, and hardware barriers in large-scale deep learning training. Conducting systematic benchmarking on Intel Xeon CPUs and NVIDIA Tesla T4 GPUs across TensorFlow and PyTorch frameworks, we evaluate four representative models—Conv6, VGG16, ResNet18, and CycleGAN. For the first time, we jointly analyze model complexity, framework-level optimizations, and hardware platforms to quantify GPU acceleration benefits, revealing that lightweight models like Conv6 achieve the most significant speedup (up to 246× in training). We also find that TensorFlow’s operator fusion reduces inference latency by approximately 15%. Using polynomial regression, we project GPU memory requirements through 2025 and argue that shared GPU infrastructure is a critical pathway toward democratizing AI and ensuring equitable research opportunities.