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Resume (English only)
Academic Achievements
- Publications:
- “FIFOAdvisor: A DSE Framework for Automated FIFO Sizing of High-Level Synthesis Designs” accepted by ASPDAC’26
- “OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs” accepted by MICRO’26
- “LaZagna: An Open-Source Framework for Flexible 3D FPGA Architectural Exploration” accepted by ICCAD’25 with Best Paper Award
- “Pieceformer: Similarity-Driven Knowledge Transfer via Scalable Graph Transformer in VLSI” accepted by MLCAD’25
- “HLS-Eval: A Benchmark and Framework for Evaluating LLMs on High-Level Synthesis Design Tasks” accepted by ICLAD’25
- “Cryptonite: Scalable Accelerator Design for Cryptographic Primitives and Algorithms” accepted by ASAP’25
- “RealProbe: An Automated and Lightweight Performance Profiler for In-FPGA Execution of High-Level Synthesis Designs” accepted by FCCM’25 with Best Paper Nomination
- Honors:
- Callie appointed to ON Semiconductor Junior Professorship
- Rishov Sarkar awarded the Oscar P. Cleaver Award
Research Experience
- Head of Sharc Lab @ Georgia Tech
- Exploring interdisciplinary research opportunities such as ML-assisted EDA, accelerators for ML, EDA-assisted accelerators, etc.
Education
Insufficient information
Background
- Research Interests: Software/hardware co-design, high-performance reconfigurable computing, graph neural network (GNN) and graph computing, electronic design automation (EDA)
- Professional Fields: FPGA, embedded system, edge computing, machine learning, EDA, etc.
- Introduction: The head of Sharc Lab @ Georgia Tech, focusing on software/hardware co-design for intelligence and efficiency.
Miscellany
- Personal Interests: Students interested in hardware design (FPGA, ASIC, etc.) and machine learning (DNNs, GNNs, etc.) are welcome to join Sharc Lab.