Scholar
Zizheng Guo
Google Scholar ID: aWkrs30AAAAJ
Ph.D. Student at Peking University
Citations & Impact
Citations
683
H-index
11
i10-index
12
Publications
20
Co-authors
43
list available
Publications
Browse publications on Google Scholar (top-right) ↗
Resume (English only)
Academic Achievements
- Published a paper on GPU-accelerated RTL simulation at the 62nd Annual Design Automation Conference (DAC) 2025, which received a Best Paper Nomination; also published a systematic approach for multi-objective double-side clock tree synthesis at the same conference; another paper addressing continuity and expressivity limitations in differentiable physical optimization was accepted to IEEE/ACM International Symposium of EDA (ISEDA) 2025; a method for handling latch loops in timing analysis with improved complexity and divergent loop detection will be presented at 2025 IEEE/ACM Design, Automation and Test in Europe (DATE); finally, contributed to iTAP: An Incremental Task Graph Partitioner for task-parallel static timing analysis, to be featured at IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC) 2025.
Research Experience
- No specific work experience or research project information listed.
Education
- BSc in Computer Science, 2018-2022, Peking University; PhD Student, 2022-, Peking University, advised by Prof. Yibo Lin.
Background
- Research interests include data structures, algorithm design, and GPU acceleration for combinatorial optimization problems in physical design automation. Currently, holds broad interest in topics like signoff timing analysis, power analysis, logic simulation, and performance-driven backend EDA tasks.
Miscellany
- Contact information: gzz@pku.edu.cn and t.me/zzguo.
