Scholar
Yichao Zhang
Google Scholar ID: XT37dl8AAAAJ
Ph.D Student, ETH Zurich
IC Design
RISC-V
Many-core
Vector Processing
B5G/6G
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Citations & Impact
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Citations
69
H-index
5
i10-index
4
Publications
13
Co-authors
17
list available
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Publications
3 items
Accelerating Precise End-to-End Simulation: Latency-Sensitive Many-core System Modeling
2026
Cited
0
TensorPool: A 3D-Stacked 8.4TFLOPS/4.3W Many-Core Domain-Specific Processor for AI-Native Radio Access Networks
2026
Cited
0
TeraPool: A Physical Design Aware, 1024 RISC-V Cores Shared-L1-Memory Scaled-up Cluster Design with High Bandwidth Main Memory Link
2026
Cited
0
Resume (English only)
Co-authors
17 total
Luca Benini
ETH Zürich, Università di Bologna
Marco Bertuletti
PhD student, ETH Zurich
Matheus Cavalcante
Stanford University
Alessandro Vanelli-Coralli
Full Professor of Telecommunications, University of Bologna, Italy
Co-author 5
Paul Scheffler
ETH Zurich
Luca Bertaccini
ETH Zurich
Frank K. Gürkaynak
Senior Scientist, ETH Zurich
