Marco Bertuletti
Scholar

Marco Bertuletti

Google Scholar ID: QoEybewAAAAJ
PhD student, ETH Zurich
computer architecturesparallel programmingwireless communications
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Citations & Impact
All-time
Citations
63
 
H-index
4
 
i10-index
3
 
Publications
20
 
Co-authors
0
 
Contact
No contact links provided.
Publications
9 items
TensorPool: A 3D-Stacked 8.4TFLOPS/4.3W Many-Core Domain-Specific Processor for AI-Native Radio Access Networks
2026
Cited
0
TeraPool: A Physical Design Aware, 1024 RISC-V Cores Shared-L1-Memory Scaled-up Cluster Design with High Bandwidth Main Memory Link
2026
Cited
0
A 410GFLOP/s, 64 RISC-V Cores, 204.8GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN
2025
Cited
0
TeraNoC: A Multi-Channel 32-bit Fine-Grained, Hybrid Mesh-Crossbar NoC for Efficient Scale-up of 1000+ Core Shared-L1-Memory Clusters
2025
Cited
0
A Dynamic Allocation Scheme for Adaptive Shared-Memory Mapping on Kilo-core RV Clusters for Attention-Based Model Deployment
2025
Cited
0
Optimizing Scalable Multi-Cluster Architectures for Next-Generation Wireless Sensing and Communication
2025
Cited
0
Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications
2025
Cited
0
Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing
2025
Cited
0
Resume (English only)
Co-authors
0 total
Co-authors: 0 (list not available)