Scholar
Samuel Bayliss
Google Scholar ID: Wt7Tt80AAAAJ
Fellow, AMD Research and Advanced Development
Citations & Impact
Citations
370
H-index
10
i10-index
11
Publications
20
Co-authors
33
list available
Publications
Resume (English only)
Academic Achievements
- An FPGA implementation of the simplex algorithm, IEEE international conference on Field Programmable Technology, Dec. 2006
- Methodology for designing statically scheduled application-specific SDRAM controllers using constrained local search, IEEE Intl. Conf. on Field Programmable Technology, Dec. 2009
- Application Specific Memory Access, Reuse and Reordering for SDRAM, Applied Reconfigurable Computing 2011, Apr 2011
- Analytical Synthesis of Bandwidth-Efficient SDRAM Address Generators, Journal of Microprocessors and Microsystems, Elsevier
- Optimizing SDRAM Bandwidth for Custom FPGA Loop Accelerators, International Symposium on Field Programmable Gate Arrays 2012, Feb 2012
- Whither Reconfigurable Computing?, Transforming Reconfigurable Systems: A Festschrift Celebrating the 60th Birthday of Professor Peter Cheung, Imperial College Press
- FPGA-based K-means Clustering Using Tree-Based Data Structures, in Proceedings of the 23rd International Conference on Field Programmable Logic and Applications (FPL'13)
- High-Level Synthesis of Dynamic Data Structures: A Case Study Using Vivado HLS
- SOAP: Structural Optimization of Arithmetic Expressions for High-Level Synthesis
- GPU vs FPGA : A comparative analysis for non-standard-precision, accepted for publication in the Proceedings of the 10th International Sympsium on Applied Reconfigurable Computing (ARC'14)
Research Experience
- EPSRC Doctoral Prize Research Fellow, Circuits and Systems Group, Electrical and Electronic Engineering Dept, Imperial College
Education
- Education background information is not provided in the given HTML content.
Background
- My research area is digital systems, with a bias towards 'customized' application-specific computation using FPGAs. Much of my work is focused more specifically on high-level synthesis techniques, memory optimization and hardware/software codesign.
Miscellany
- Contact information and personal website details are available.
