Scholar
Paul V. Gratz
Google Scholar ID: O9teRZsAAAAJ
Department of Electrical and Computer Engineering, Texas A&M University
Citations & Impact
Citations
1,706
H-index
22
i10-index
46
Publications
20
Co-authors
84
list available
Contact
No contact links provided.
Publications
Resume (English only)
Academic Achievements
- Paper 'Synchronized Progress in Interconnection Networks (SPIN): A New Theory for Deadlock Freedom' was selected as a Top Pick from the architecture conferences in 2018 by IEEE Micro. Papers 'Path Confidence based Lookahead Prefetching' and 'B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors' were nominated for best papers at MICRO '16 and MICRO '14 respectively. Received a best paper award for 'An Evaluation of the TRIPS Computer System' at ASPLOS '09. Awarded the 'Distinguished Achievement Award in Teaching – College Level' from the Texas A&M Association of Former Students in 2016, and the 'Excellence Award in Teaching, 2017' from the Texas A&M College of Engineering.
Research Experience
- Worked as a design engineer with Intel Corporation from 1997 to 2002. Currently, a Professor in the Department of Electrical and Computer Engineering at Texas A&M University, leading the Computer Engineering and Systems Group.
Education
- Received B.S. and M.S. degrees in Electrical Engineering from The University of Florida in 1994 and 1997 respectively. Obtained Ph.D. degree in Electrical and Computer Engineering from the University of Texas at Austin in 2008.
Background
- Research interests include efficient, secure and reliable design in the context of high performance computer architecture, processor memory systems, and on-chip interconnection networks.
