ORAP: Optimized Row Access Prefetching for Rowhammer-mitigated Memory

2026-02-13

AI Summary

This work proposes ORAP, a novel prefetcher that jointly optimizes prefetching strategies and Rowhammer mitigation for the first time. By caching DRAM row buffer contents in the last-level cache (LLC), ORAP significantly reduces redundant row activations. It integrates LLC management, the Berti prefetcher, and DDR5-native Rowhammer countermeasures to enable row-activation-aware prefetching. Experimental results demonstrate that, under Refresh Management (RFM), ORAP reduces DRAM activation rates by 51.3% and improves performance by 4.6% compared to Berti+SPP-PPF. Under Probabilistic Row Activation Counting (PRAC), ORAP further reduces energy overhead by 11.8%. These gains highlight ORAP’s effectiveness in reconciling the tension between aggressive prefetching and Rowhammer protection.

Technology Category

• Machine Learning: Hardware-aware ML
• Humans and AI: Human-Aware Planning and Behavior Prediction
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems

Application Category

• Search and Retrieval-Augmented AI: Retrieval-Augmented Generation (RAG) and multi-modal RAG
• Responsible Web: Data and user privacy-enhancing technologies for the Web
• Security and Privacy: Privacy-enhancing technologies

Abstract

Rowhammer is a well-studied DRAM phenomenon wherein multiple activations to a given row can cause bit flips in adjacent rows. Many mitigation techniques have been introduced to address Rowhammer, with some support being incorporated into the JEDEC DDR5 standard for per-row-activation-counter (PRAC) and refresh-management (RFM) systems. Mitigation schemes built on these mechanisms claim to have various levels of area, power, and performance overheads. To date the evaluation of existing mitigation schemes typically neglects the impact of other memory system components such as hardware prefetchers. Nearly all modern systems incorporate hardware prefetching and these can significantly improve processor performance through speculative cache population. These prefetchers induce higher numbers of downstream memory requests and increase DRAM activation rates. The performance overhead of Rowhammer mitigations are tied directly to memory access patterns, exposing both hardware prefetchers and Rowhammer mitigations to cross-interaction. We find that the performance improvement provided by prior-work hardware prefetchers is often severely impacted by Rowhammer mitigations. In effect, much of the benefit of speculative memory references from prefetching lies in accelerating and reordering DRAM references in ways that trigger mitigations, significantly reducing the benefits of prefetching. This work proposes the Optimized Row Access Prefetcher (ORAP), leveraging last-level-cache (LLC) space to cache large portions of DRAM rowbuffer contents to reduce the need for future activations. Working with the state-of-the-art Berti prefetcher, ORAP reduces DRAM activation rates by 51.3% and achieves a 4.6% speedup over the prefetcher configuration of Berti and SPP-PPF when prefetching in an RFM-mitigated memory system. Under PRAC mitigations, ORAP reduces energy overheads by 11.8%.

Problem

• Rowhammer
• hardware prefetching
• DRAM activation
• memory system interaction
• performance overhead

Innovation

• Rowhammer mitigation
• hardware prefetching
• DRAM activation reduction
• last-level cache optimization
• memory system co-design