Recipient of the 2023 ACM SIGARCH Maurice Wilkes Award for contributions to memory address translation in commercial microprocessors and OSes.
Best Paper Award at ISCA ’23 and Distinguished Paper Award at ASPLOS ’23.
Six papers selected for IEEE’s Top Picks in Computer Architecture, with two honorable mentions.
Two papers included in ISCA’s 50th Anniversary Retrospective Volume for lasting impact.
Received Yale College’s 2025 Dylan Hixon ’88 Prize for teaching excellence in natural sciences and the 2022 Ackerman Award for engineering teaching.
Key projects include HALO and SCALO BCI chips; publications at top venues including SOSP’25, ASPLOS’23, and Hot Chips’22.
Background
Works on making computer systems more efficient—both by increasing execution speed and by improving programmer productivity—to better support advanced AI and neurotechnology.
Core expertise is in computer architecture; also designs operating systems, compilers, and chips to achieve these goals.
His research group highlighted the growing overhead of memory address translation and developed widely adopted optimizations.
Ideas on coalesced TLBs and translation contiguity have been integrated by AMD, NVIDIA, RISC-V, Meta, and Linux into billions of microprocessors and operating systems.
Authored a book on virtual memory and contributed to the appendix of the classic quantitative computer architecture textbook.
Builds computer systems for brain-computer interfaces (BCIs) to advance neurological treatments and understanding of brain function through projects like HALO and SCALO.