CounterPoint: Using Hardware Event Counters to Refute and Refine Microarchitectural Assumptions (Extended Version)

2026-01-03

AI Summary

Accurate characterization of microarchitectural behavior using hardware performance counters is hindered by ambiguous specifications, opaque designs, and multiplexing-induced noise, impeding experts’ ability to validate hypotheses. This work proposes CounterPoint, a framework that for the first time systematically integrates formal microarchitectural models—represented as μ-path decision diagrams—with noisy performance counter data. By comparing multidimensional confidence regions derived from the model against observed hardware events, CounterPoint automatically detects inconsistencies and pinpoints potential undocumented microarchitectural features. Applied to Intel Haswell’s memory management unit, the approach successfully uncovers several previously undisclosed mechanisms, including a load-store queue–side TLB prefetcher, a mergeable page table walker, and an abortable page table walk capability.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Agent Architectures
• Data Mining & Knowledge Management: Intelligent Query Processing

Application Category

• User Modeling, Personalization and Recommendation: Attacks and countermeasures in recommendation systems
• Security and Privacy: Tracking, profiling, and countermeasures against them
• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization

Abstract

Hardware event counters offer the potential to reveal not only performance bottlenecks but also detailed microarchitectural behavior. In practice, this promise is undermined by their vague specifications, opaque designs, and multiplexing noise, making event counter data hard to interpret. We introduce CounterPoint, a framework that tests user-specified microarchitectural models - expressed as $μ$path Decision Diagrams - for consistency with performance counter data. When mismatches occur, CounterPoint pinpoints plausible microarchitectural features that could explain them, using multi-dimensional counter confidence regions to mitigate multiplexing noise. We apply CounterPoint to the Haswell Memory Management Unit as a case study, shedding light on multiple undocumented and underdocumented microarchitectural behaviors. These include a load-store queue-side TLB prefetcher, merging page table walkers, abortable page table walks, and more. Overall, CounterPoint helps experts reconcile noisy hardware performance counter measurements with their mental model of the microarchitecture - uncovering subtle, previously hidden hardware features along the way.

Problem

• hardware event counters
• microarchitectural assumptions
• performance counter interpretation
• multiplexing noise
• undocumented microarchitectural behaviors

Innovation

• hardware event counters
• microarchitectural modeling
• μ-path Decision Diagrams
• multiplexing noise mitigation
• memory management unit