Advancing Routing-Awareness in Analog ICs Floorplanning

2025-10-17

AI Summary

Existing learning-based approaches for analog IC floorplanning suffer from strong coupling between floorplanning and routing, and lack explicit routing awareness. Method: This paper proposes an automated floorplanning engine integrating reinforcement learning (RL) with relational graph convolutional networks (R-GCN). It introduces high-resolution grid partitioning, precise pin modeling, and a dynamic routing-resource estimation algorithm to explicitly model congestion evolution during training. Contribution/Results: To the best of our knowledge, this is the first learning-based framework achieving joint optimization of routability and area efficiency. Experiments demonstrate that, compared to state-of-the-art learning methods, the proposed approach reduces dead space by 13.8%, total wirelength by 40.6%, and improves routing success rate by 73.4%, meeting industrial usability requirements.

Technology Category

• Planning, Routing, and Scheduling: Planning/Scheduling and Learning
• Search and Optimization: Learning to Search
• Intelligent Robots: Learning & Optimization for ROB

Application Category

• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking
• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications

Abstract

The adoption of machine learning-based techniques for analog integrated circuit layout, unlike its digital counterpart, has been limited by the stringent requirements imposed by electric and problem-specific constraints, along with the interdependence of floorplanning and routing steps. In this work, we address a prevalent concern among layout engineers regarding the need for readily available routing-aware floorplanning solutions. To this extent, we develop an automatic floorplanning engine based on reinforcement learning and relational graph convolutional neural network specifically tailored to condition the floorplan generation towards more routable outcomes. A combination of increased grid resolution and precise pin information integration, along with a dynamic routing resource estimation technique, allows balancing routing and area efficiency, eventually meeting industrial standards. When analyzing the place and route effectiveness in a simulated environment, the proposed approach achieves a 13.8% reduction in dead space, a 40.6% reduction in wirelength and a 73.4% increase in routing success when compared to past learning-based state-of-the-art techniques.

Problem

• Addressing routing-aware floorplanning for analog ICs
• Developing reinforcement learning-based automatic floorplanning engine
• Balancing routing efficiency and area usage in layouts

Innovation

• Reinforcement learning for analog IC floorplanning
• Relational graph convolutional network enhances routability
• Dynamic routing resource estimation balances efficiency