TOPCELL: Topology Optimization of Standard Cell via LLMs

2026-04-14

AI Summary

This work addresses the challenge of transistor topology optimization in standard cell design at advanced process nodes, where high computational complexity renders traditional exhaustive search methods infeasible. The authors propose the first integration of large language models (LLMs) into this task by formulating it as a conditional generation problem and fine-tuning the model using Group Relative Policy Optimization (GRPO) to produce topologies that satisfy both logical functionality and physical layout constraints. The approach demonstrates zero-shot generalization and integrates seamlessly into industrial place-and-route flows. Experimental results show that, at the 7nm node, the method achieves layout quality comparable to an exhaustive solver while accelerating runtime by 85.91×; at the 2nm node, it significantly outperforms baseline models, enabling scalable, physically aware, and efficient topology generation.

Technology Category

• Search and Optimization: Learning to Search
• Planning, Routing, and Scheduling: Planning with Language Models
• Machine Learning: Large Multimodal Models (LMMs)

Application Category

• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs
• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems
• User Modeling, Personalization and Recommendation: Large Language Models (LLM) for user modeling and recommendation

Abstract

Transistor topology optimization is a critical step in standard cell design, directly dictating diffusion sharing efficiency and downstream routability. However, identifying optimal topologies remains a persistent bottleneck, as conventional exhaustive search methods become computationally intractable with increasing circuit complexity in advanced nodes. This paper introduces TOPCELL, a novel and scalable framework that reformulates high-dimensional topology exploration as a generative task using Large Language Models (LLMs). We employ Group Relative Policy Optimization (GRPO) to fine-tune the model, aligning its topology optimization strategy with logical (circuit) and spatial (layout) constraints. Experimental results within an industrial flow targeting an advanced 2nm technology node demonstrate that TOPCELL significantly outperforms foundation models in discovering routable, physically-aware topologies. When integrated into a state-of-the-art (SOTA) automation flow for a 7nm library generation task, TOPCELL exhibits robust zero-shot generalization and matches the layout quality of exhaustive solvers while achieving an 85.91x speedup.

Problem

• topology optimization
• standard cell
• transistor topology
• routability
• diffusion sharing

Innovation

• Topology Optimization
• Large Language Models (LLMs)
• Standard Cell Design
• Group Relative Policy Optimization (GRPO)
• Zero-shot Generalization