The Power of Graph Signal Processing for Chip Placement Acceleration

2025-02-24

AI Summary

VLSI placement faces challenges of high computational complexity and slow convergence in nonlinear optimization. Existing GCN-based deep learning methods rely heavily on large-scale labeled data and prolonged training, limiting generalizability. This paper proposes GiFt, a training-free, parameter-free graph signal processing framework that leverages circuit netlist topology as structural prior. GiFt employs multi-resolution graph filtering to efficiently smooth and model placement signals, thereby accelerating the convergence of analytical placers without supervision. Crucially, GiFt eliminates the need for any training or hyperparameter tuning, drastically lowering deployment overhead. Experiments demonstrate that GiFt reduces total runtime by over 45% compared to the GPU-accelerated state-of-the-art placer DREAMPlace, while maintaining or even improving placement quality—achieving, for the first time, training-free, high-efficiency, high-quality, graph-structure-driven placement optimization. Both algorithmic design and empirical performance set new state-of-the-art benchmarks.

Technology Category

• Machine Learning: Graph-based Machine Learning
• Computer Vision: Learning & Optimization for CV
• Search and Optimization: Learning to Search

Application Category

• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking
• Systems and Infrastructure for Web, Mobile and WoT: Experiences and lessons learnt from Web-based algorithms and system deployments

Abstract

Placement is a critical task with high computation complexity in VLSI physical design. Modern analytical placers formulate the placement objective as a nonlinear optimization task, which suffers a long iteration time. To accelerate and enhance the placement process, recent studies have turned to deep learning-based approaches, particularly leveraging graph convolution networks (GCNs). However, learning-based placers require time- and data-consuming model training due to the complexity of circuit placement that involves large-scale cells and design-specific graph statistics. This paper proposes GiFt, a parameter-free technique for accelerating placement, rooted in graph signal processing. GiFt excels at capturing multi-resolution smooth signals of circuit graphs to generate optimized placement solutions without the need for time-consuming model training, and meanwhile significantly reduces the number of iterations required by analytical placers. Experimental results show that GiFt significantly improving placement efficiency, while achieving competitive or superior performance compared to state-of-the-art placers. In particular, compared to DREAMPlace, the recently proposed GPU-accelerated analytical placer, GF-Placer improves total runtime over 45%.

Problem

• Accelerate VLSI chip placement
• Reduce model training time
• Enhance placement efficiency

Innovation

• Graph signal processing technique
• Parameter-free acceleration method
• Multi-resolution signal capture