🤖 AI Summary
This work addresses the limitations of existing chip placement generation models, which often rely on randomly synthesized data, suffer from low sampling efficiency, and frequently produce overlapping layouts. To overcome these challenges, the authors propose FlowPlace, a novel approach that integrates mask-guided synthetic data generation, a flow-matching training framework capable of incorporating flexible priors, and a hard-constrained sampling strategy that guarantees zero overlap. Evaluated on the OpenROAD and ICCAD 2015 benchmarks, FlowPlace significantly outperforms current state-of-the-art methods, achieving zero-overlap placements while accelerating sampling by 10–50× and delivering superior PPA (power, performance, and area) metrics.
📝 Abstract
Chip placement plays an important role in physical design. While generative models like diffusion models offer promising learning-based solutions, current methods have the following limitations: they use random synthetic data for pre-training, require long sampling times, and often result in overlaps due to their dependence on gradient-based solvers during the sampling process. To overcome these issues, we propose FlowPlace, which features mask-guided synthetic data generation, flow-based efficient training with flexible prior injection, and hard constraint sampling for overlap-free layouts. Experiments on OpenROAD and ICCAD 2015 benchmarks show FlowPlace achieves better PPA metrics, 10-50$\times$ faster sampling efficiency, and zero overlaps.