System-Technology Co-Optimization of Bitline Routing and Bonding Pathways in Monolithic 3D DRAM Architectures

2026-03-12

AI Summary

This work addresses the challenges of reduced sensing margin, increased latency, and degraded array efficiency in 3D DRAM caused by bitline routing congestion and limited hybrid bonding paths. To overcome these limitations, the authors propose a system–process co-optimization approach that, for the first time, integrates amorphous oxide semiconductor (AOS) selectors with a bitline-banded architecture to enable efficient routing and co-designed bonding pathways within CMOS-bonded arrays. Leveraging TCAD-extracted device characteristics and parasitic parameters, SPICE simulations demonstrate significant performance improvements: the design achieves a bit density of 2.6 Gb/mm²—approximately six times that of D1b 2D DRAM—a row cycle time reduced to 10.5 ns (a 51% improvement over D1b’s 21.3 ns), and a 60% reduction in read/write energy consumption.

Technology Category

• Search and Optimization: Distributed Search
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Machine Learning: Hardware-aware ML

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Data management and stream processing for Web, mobile and wireless applications
• Search and Retrieval-Augmented AI: Vertical and domain-specific search
• Responsible Web: Data and user privacy-enhancing technologies for the Web

Abstract

3D DRAM has emerged as a promising approach for continued density scaling, but its viability is limited by routing and hybrid bonding constraints to periphery, which may degrade sensing margin, latency, and array efficiency. With device characteristics and array parasitics extracted from TCAD, SPICE simulations are performed with peri logic in a CMOS-Bonded-Array (CBA). The analysis shows that the bitline strap architecture with amorphous oxide semiconductor (AOS) selectors is essential to manage routing congestion and parasitics. The optimized design achieves a bit density of 2.6 Gb/mm^2 (137 layers with Si access transistors or 87 layers with AOS), representing ~6x density scaling over D1b 2D DRAM. The design further demonstrates a nominal row cycle time (tRC) of 10.5 ns, compared to 21.3 ns in D1b, and a 60% reduction in read/write energy.

Problem

• 3D DRAM
• bitline routing
• hybrid bonding
• array efficiency
• parasitics

Innovation

• System-Technology Co-Optimization
• Monolithic 3D DRAM
• Amorphous Oxide Semiconductor (AOS)
• Bitline Strap Architecture
• Hybrid Bonding