Synchronous Signal Temporal Logic for Decidable Verification of Cyber-Physical Systems

2026-03-26

AI Summary

Signal Temporal Logic (STL) is generally undecidable for static verification, limiting its applicability in safety-critical cyber-physical systems (CPS). This work proposes Synchronous Signal Temporal Logic (SSTL), a decidable fragment of STL obtained by introducing the Signal Invariance Hypothesis (SIH) and a fixed-time sampling mechanism. We formally define SSTL for the first time and prove that SIH is both necessary and sufficient for semantic equivalence between STL and SSTL. Furthermore, we reduce SSTL specifications to predicate Linear Temporal Logic (LTLₚ), enabling automated verification via the SPIN model checker. The approach has been successfully applied to complex CPS benchmarks, including a 33-node human heart model, demonstrating decidable static verification of both safety and liveness properties.

Technology Category

• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Reasoning under Uncertainty: Stochastic Optimization

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications
• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems
• Semantics and Knowledge: Data modeling to support human-machine intelligence, including LLMs agents, intelligent system behavior, explanations, and user-friendly interactions

Abstract

Many Cyber Physical System (CPS) work in a safety-critical environment, where correct execution, reliability and trustworthiness are essential. Signal Temporal Logic (STL) provides a formal framework for checking safety-critical CPS. However, static verification of STL is undecidable in general, except when we want to verify using run-time-based methods, which have limitations. We propose Synchronous Signal Temporal Logic (SSTL), a decidable fragment of STL, which admits static safety and liveness property verification. In SSTL, we assume that a signal is sampled at fixed discrete steps, called ticks, and then propose a hypothesis, called the Signal Invariance Hypothesis (SIH), which is inspired by a similar hypothesis for synchronous programs. We define the syntax and semantics of SSTL and show that SIH is a necessary and sufficient condition for equivalence between an STL formula and its SSTL counterpart. By translating SSTL to LTL_P (LTL defined over predicates), we enable decidable model checking using the SPIN model checker. We demonstrate the approach on a 33-node human heart model and other case studies.

Problem

• Cyber-Physical Systems
• Signal Temporal Logic
• Decidable Verification
• Static Verification
• Formal Verification

Innovation

• Synchronous Signal Temporal Logic
• Signal Invariance Hypothesis
• Decidable Verification
• Cyber-Physical Systems
• Model Checking