CHORUS: Complementary Experts for High-Coverage Testbench Stimulus Generation

2026-08-10

AI Summary

This work addresses the inefficiency of generating high-coverage test stimuli in hardware verification by proposing the CHORUS framework. CHORUS first obtains behaviorally diverse model checkpoints through staged supervised fine-tuning, then transforms them into complementary experts via dense-reward reinforcement learning, and finally integrates these experts into a single model using training-agnostic merging or post-training techniques. This approach is the first to systematically leverage behavioral diversity emerging during fine-tuning to construct complementary experts, thereby overcoming the performance bottleneck inherent in conventional SFT→RL pipelines. The resulting consolidated 4B-parameter model achieves 88.0% Pass@1 on CVDP-ECov, surpassing the 671B-parameter DeepSeek-R1 by a substantial margin of 13.5 percentage points.

Abstract

Large language models (LLMs) have advanced code generation, where executable feedback provides a more reliable learning signal than textual imitation alone. Hardware verification is an important application of code generation and accounts for a substantial fraction of modern chip design effort, with high-coverage testbench stimulus generation as a key task. We present CHORUS, a post-training framework that pushes performance beyond what a conventional supervised fine-tuning (SFT)-to-reinforcement learning (RL) pipeline achieves. CHORUS builds on two observations. First, staged SFT produces behaviorally diverse checkpoints, and dense-reward RL turns them into strong experts with comparable aggregate performance but distinct task-level strengths. Second, these complementary strengths can be exploited through either training-free model merging or further post-training to outperform the best individual expert. By consolidating the resulting specialists into a single 4B model, CHORUS achieves 88.0% Pass@1 on CVDP-ECov, outperforming DeepSeek-R1 (671B) by 13.5 percentage points.

Problem

• hardware verification
• testbench stimulus generation
• high-coverage
• code generation
• chip design

Innovation

• CHORUS
• complementary experts
• staged SFT
• dense-reward RL
• model merging