🤖 AI Summary
This work addresses the critical limitation of current large language models (LLMs) in generating RTL code that, while functionally correct, largely neglects key physical design objectives such as power, performance, and area (PPA). To bridge this gap, the authors propose a multi-agent, closed-loop optimization framework integrated with EDA tools, featuring three collaborative agents—programmer, correctness verifier, and PPA optimizer—that jointly enhance PPA metrics without compromising functional correctness. The core innovation lies in a novel, evolvable structured external memory mechanism that dynamically stores and reuses optimization experiences, enabling continuous policy improvement without model retraining. This approach represents the first effort to deeply embed PPA awareness into LLM-driven RTL generation, demonstrating strong scalability and effectiveness in real-world hardware design scenarios.
📝 Abstract
LLMs have recently demonstrated strong capabilities in automatic RTL code generation, achieving high syntactic and functional correctness. However, most methods focus on functional correctness while overlooking critical physical design objectives, including Power, Performance, and Area. In this work, we propose a PPA-aware, tool-integrated multi-agent framework for high-quality verilog code generation. Our framework explicitly incorporates EDA tools into a closed-loop workflow composed of a \textit{Programmer Agent}, a \textit{Correctness Agent}, and a \textit{PPA Agent}, enabling joint optimization of functional correctness and physical metrics. To support continuous improvement without model retraining, we introduce an \textit{Evolved Memory Mechanism} that externalizes optimization experience into structured memory nodes. A dedicated memory manager dynamically maintains the memory pool and allows the system to refine strategies based on historical execution trajectories. Extensive experiments demonstrate that our approach achieves strong functional correctness while delivering significant improvements in PPA metrics. By integrating tool-driven feedback with structured and evolvable memory, our framework transforms RTL generation from one-shot reasoning into a continual, feedback-driven optimization process, providing a scalable pathway for deploying LLMs in real-world hardware design flows.