Functional ISS-Driven Verification of Superscalar RISC-V Processors

2024-07-30

International Conference on Electronics, Circuits, and Systems

AI Summary

Functional verification of superscalar RISC-V processors faces a fundamental trade-off between coverage completeness and simulation efficiency. Method: This paper proposes SupeRFIVe, the first ISS-driven, scalable verification framework that enables real-time co-simulation between an instruction-set simulator (ISS) and RTL design via a socket-based interface. It supports full-scenario functional verification of dual-issue superscalar CPUs, integrating Spike ISS, a SystemVerilog/UVM testbench, and open-source benchmarks (e.g., CoreMark, Dhrystone). Contribution/Results: Experiments demonstrate over 40% reduction in verification cycle time compared to conventional approaches. Coverage of critical pipeline exceptions and concurrent execution paths is significantly improved, while maintaining zero false positives—effectively breaking the longstanding precision–performance trade-off barrier in RISC-V processor verification.

Technology Category

• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Computer Vision: Image and Video Retrieval
• Machine Learning: Hardware-aware ML

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Virtualization and resource management in Web systems and infrastructures
• Security and Privacy: Large-scale security measurements
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines

Abstract

A time-efficient and comprehensive verification is a fundamental part of the design process for modern computing platforms, and it becomes ever more important and critical to optimize as the latter get ever more complex. SupeRFIVe is a methodology for the functional verification of superscalar processors that leverages an instruction set simulator to validate their correctness according to a simulation-based approach, interfacing a testbench for the design under test with the instruction set simulator by means of socket communication. We demonstrate the effectiveness of the SupeRFIVe methodology by applying it to verify the functional correctness of a RISC-V dual-issue superscalar CPU, leveraging the state-of-the-art RISCV instruction set simulator Spike and executing a set of benchmark applications from the open literature.

Problem

• RISC-V
• Superscalar Processor
• Instruction Set Simulation

Innovation

• SupeRFIVe
• RISC-V Superscalar Processors
• Instruction Set Simulator (ISS)