Monolithic 3D FPGAs Utilizing Back-End-of-Line Configuration Memories

2025-01-12

AI Summary

To address area, latency, and power bottlenecks of conventional FPGAs in hyperdimensional computing and large language model (LLM) workloads, this paper presents the first monolithic three-dimensional programmable gate array (3D FPGA) fabricated using back-end-of-line (BEOL) integration. Our approach innovatively employs amorphous oxide semiconductor (AOS) transistors—n-type W-In₂O₃ and p-type SnO—to implement low-leakage configuration memory, while vertically stacking programmable switch and routing matrices atop logic units to enable logic–routing co-optimization in the vertical dimension. Leveraging TCAD modeling, 7 nm process compatibility, and a restructured VTR toolchain, we evaluate the architecture on hyperdimensional computing and LLM benchmarks. Results show a 3.4× reduction in area–delay² (AT²), a 27% decrease in critical-path delay, and a 26% reduction in power consumption of reconfigurable routing units compared to state-of-the-art 2D FPGAs.

Technology Category

• Machine Learning: Hardware-aware ML
• Computer Vision: 3D Computer Vision
• Search and Optimization: Learning to Search

Application Category

• Economics, Online Markets and Human Computation: Architectures and workflows that use LLMs for crowd work
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs
• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications

Abstract

This work presents a novel monolithic 3D (M3D) FPGA architecture that leverages stackable back-end-of-line (BEOL) transistors to implement configuration memory and pass gates, significantly improving area, latency, and power efficiency. By integrating n-type (W-doped In_2O_3) and p-type (SnO) amorphous oxide semiconductor (AOS) transistors in the BEOL, Si SRAM configuration bits are substituted with a less leaky equivalent that can be programmed at logic-compatible voltages. BEOL-compatible AOS transistors are currently under extensive research and development in the device community, with investment by leading foundries, from which reported data is used to develop robust physics-based models in TCAD that enable circuit design. The use of AOS pass gates reduces the overhead of reconfigurable circuits by mapping FPGA switch block (SB) and connection block (CB) matrices above configurable logic blocks (CLBs), thereby increasing the proximity of logic elements and reducing latency. By interfacing with the latest Verilog-to-Routing (VTR) suite, an AOS-based M3D FPGA design implemented in 7 nm technology is demonstrated with 3.4x lower area-time squared product (AT^2), 27% lower critical path latency, and 26% lower reconfigurable routing block power on benchmarks including hyperdimensional computing and large language models (LLMs).

Problem

• 3D FPGA
• AOS Transistors
• High-Dimensional Computing

Innovation

• 3D FPGA
• AOS Transistors
• Enhanced Efficiency