FASE: FPGA-Assisted Syscall Emulation for Rapid End-to-End Processor Performance Validation

2025-09-10

AI Summary

To address the long verification cycles and RTL/SoC integration dependency in early microarchitectural performance validation, this paper proposes an FPGA-accelerated system call simulation framework—the first to enable transparent cross-device system call delegation on FPGA. Methodologically, it introduces a lightweight CPU interface, a custom Host-Target Protocol (HTP), and a host-side remote runtime, enabling multithreaded benchmarks to execute directly on RISC-V SMP processor prototypes—without OS support or full SoC integration. Key contributions include: (1) the first FPGA-level system call simulation architecture; (2) co-optimization of protocol and runtime to minimize inter-platform communication overhead; and (3) sub-1% single-thread performance error and >2000× speedup over Proxy Kernel; multithreaded validation achieves >91.5% accuracy. The framework significantly shortens design iteration cycles and reduces verification complexity.

Technology Category

• Multiagent Systems: Agent Communication
• Cognitive Modeling & Cognitive Systems: Agent Architectures
• Machine Learning: Hardware-aware ML

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Security and Privacy: Large-scale security measurements
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics

Abstract

The rapid advancement of AI workloads and domain-specific architectures has led to increasingly diverse processor microarchitectures, whose design exploration requires fast and accurate performance validation. However, traditional workflows defer validation process until RTL design and SoC integration are complete, significantly prolonging development and iteration cycle. In this work, we present FASE framework, FPGA-Assisted Syscall Emulation, the first work for adapt syscall emulation on FPGA platforms, enabling complex multi-thread benchmarks to directly run on the processor design without integrating SoC or target OS for early-stage performance validation. FASE introduces three key innovations to address three critical challenges for adapting FPGA-based syscall emulation: (1) only a minimal CPU interface is exposed, with other hardware components untouched, addressing the lack of a unified hardware interface in FPGA systems; (2) a Host-Target Protocol (HTP) is proposed to minimize cross-device data traffic, mitigating the low-bandwidth and high-latency communication between FPGA and host; and (3) a host-side runtime is proposed to remotely handle Linux-style system calls, addressing the challenge of cross-device syscall delegation. Experiments ware conducted on Xilinx FPGA with open-sourced RISC-V SMP processor Rocket. With single-thread CoreMark, FASE introduces less than 1% performance error and achieves over 2000x higher efficiency compared to Proxy Kernel due to FPGA acceleration. With complex OpenMP benchmarks, FASE demonstrates over 96% performance validation accuracy for most single-thread workloads and over 91.5% for most multi-thread workloads compared to full SoC validation, significantly reducing development complexity and time-to-feedback. All components of FASE framework are released as open-source.

Problem

• Accelerating processor performance validation for diverse microarchitectures
• Enabling early-stage validation without full SoC integration
• Addressing FPGA-host communication challenges in syscall emulation

Innovation

• FPGA-assisted syscall emulation for early validation
• Host-Target Protocol minimizes cross-device data traffic
• Host-side runtime handles cross-device system calls