LAsset: An LLM-assisted Security Asset Identification Framework for System-on-Chip (SoC) Verification

2026-01-06

arXiv.org

AI Summary

This work addresses the growing inefficiency of pre-silicon verification methods that rely on manual identification of security assets in modern SoCs and IP blocks, a process hindered by escalating design complexity and heavy dependence on expert knowledge. To overcome this limitation, the paper introduces LAsset, a novel framework that pioneers the integration of large language models (LLMs) into hardware security. LAsset automatically extracts primary and secondary security assets from design specifications and RTL code by jointly performing structural analysis, semantic understanding, and inter-module dependency modeling, thereby constructing cross-module security dependency graphs. The approach enables end-to-end automated asset identification from specification documents to implementation, achieving recall rates of 90% and 93% on SoC and IP designs, respectively, significantly enhancing scalability while drastically reducing manual effort.

Technology Category

• Machine Learning: Hardware-aware ML
• Natural Language Processing: Safety and Robustness
• Application Domains: Security

Application Category

• Security and Privacy: Large-scale security measurements
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs

Abstract

The growing complexity of modern system-on-chip (SoC) and IP designs is making security assurance difficult day by day. One of the fundamental steps in the pre-silicon security verification of a hardware design is the identification of security assets, as it substantially influences downstream security verification tasks, such as threat modeling, security property generation, and vulnerability detection. Traditionally, assets are determined manually by security experts, requiring significant time and expertise. To address this challenge, we present LAsset, a novel automated framework that leverages large language models (LLMs) to identify security assets from both hardware design specifications and register-transfer level (RTL) descriptions. The framework performs structural and semantic analysis to identify intra-module primary and secondary assets and derives inter-module relationships to systematically characterize security dependencies at the design level. Experimental results show that the proposed framework achieves high classification accuracy, reaching up to 90% recall rate in SoC design, and 93% recall rate in IP designs. This automation in asset identification significantly reduces manual overhead and supports a scalable path forward for secure hardware development.

Problem

• Security Asset Identification
• System-on-Chip (SoC)
• Pre-silicon Verification
• Hardware Security
• IP Design

Innovation

• LLM-assisted
• security asset identification
• SoC verification
• RTL analysis
• automated threat modeling