Testing and Fault Tolerance Techniques for Carbon Nanotube-Based FPGAs

2025-08-27

AI Summary

Carbon nanotube (CNT)-based FPGAs suffer from interconnect delay faults induced by process variations and logic block failures caused by metallic CNTs (m-CNTs). Method: This work proposes a systematic test-and-tolerance framework integrating ring-oscillator-based delay testing, a 6-input LUT accelerated test structure, dedicated carry-chain testing, an m-CNT-aware CLB diagnosis algorithm, and a shared redundant row repair architecture—enhanced by process-variation-aware fault modeling for precise fault localization and mitigation. Results: Experimental evaluation demonstrates a 35.49% reduction in LUT test time, high fault coverage, and low hardware overhead. The redundancy architecture effectively masks faulty units, significantly improving chip yield and reliability. This work establishes a scalable, co-designed test-and-tolerance paradigm enabling practical deployment of CNT-FPGAs.

Technology Category

• Machine Learning: Hardware-aware ML
• Constraint Satisfaction and Optimization: Distributed CSP/Optimization
• Computer Vision: Adversarial Attacks & Robustness

Application Category

• Responsible Web: Measurement, analysis, and circumvention of Web censorship
• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs

Abstract

As the semiconductor manufacturing process technology node shrinks into the nanometer-scale, the CMOS-based Field Programmable Gate Arrays (FPGAs) face big challenges in scalability of performance and power consumption. Multi-walled Carbon Nanotube (MWCNT) serves as a promising candidate for Cu interconnects thanks to the superior conductivity. Moreover, Carbon Nanotube Field Transistor (CNFET) also emerges as a prospective alternative to the conventional CMOS device because of high power efficiency and large noise margin. The combination of MWCNT and CNFET enables the promising CNT-based FPGAs. However, the MWCNT interconnects exhibit significant process variations due to immature fabrication process, leading to delay faults. Also, the non-ideal CNFET fabrication process may generate a few metallic CNTs (m-CNTs), rendering correlated faulty blocks. In this article, we propose a ring oscillator (RO) based testing technique to detect delay faults due to the process variation of MWCNT interconnects. Furthermore, we propose an effective testing technique for the carry chains in CLBs, and an improved circuit design based on the lookup table (LUT) is applied to speed up the fault testing of CNT-based FPGAs. In addition, we propose a testing algorithm to detect m-CNTs in CLBs. Finally, we propose a redundant spare row sharing architecture to improve the yield of CNT-based FPGA further. Experimental results show that the test time for a 6-input LUT can be reduced by 35.49% compared with conventional testing, and the proposed algorithm can achieve a high test coverage with little overhead. The proposed redundant architecture can repair the faulty segment effectively and efficiently.

Problem

• Detecting delay faults in carbon nanotube FPGA interconnects
• Testing carry chains and lookup tables for fault detection
• Identifying metallic CNTs causing correlated faulty blocks

Innovation

• Ring oscillator testing for MWCNT delay faults
• Improved LUT design for faster fault testing
• Redundant spare row sharing for yield improvement