X-HEEP: An Open-Source, Configurable and Extendible RISC-V Platform for TinyAI Applications

2025-08-23

AI Summary

Open-source, configurable RISC-V platforms tailored for ultra-low-power edge AI (TinyAI) remain scarce. Method: This paper proposes an extensible hardware architecture supporting flexible integration of heterogeneous accelerators, centered on the eXtendible Accelerator InterFace (XAIF)—a novel interface enabling seamless accelerator integration and multi-scenario configuration. The design leverages FPGA prototyping, ASIC implementation, and SystemC-RTL co-modeling to enable deep customization of processor cores, memory, interconnects, and peripherals. Results: Implemented in TSMC 65 nm CMOS, the chip occupies only 0.15 mm² and exhibits a leakage power of just 29 μW. When integrated with a near-memory accelerator, it achieves a 7.3× speedup and a 3.6× improvement in energy efficiency. This platform delivers an open-source, configurable, and scalable system-level solution for TinyAI applications.

Technology Category

• Machine Learning: Hardware-aware ML
• Humans and AI: Explainable AI (XAI) for Human Understanding
• Cognitive Modeling & Cognitive Systems: Agent Architectures

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications
• Security and Privacy: Security and privacy of machine learning and AI applications
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines

Abstract

In this work, we present X-HEEP, an open-source, configurable, and extendible RISC-V platform for ultra-low-power edge applications (TinyAI). X-HEEP features the eXtendible Accelerator InterFace (XAIF), which enables seamless integration of accelerators with varying requirements along with an extensive internal configuration of cores, memory, bus, and peripherals. Moreover, it supports various development flows, including FPGA prototyping, ASIC implementation, and mixed SystemC-RTL modeling, enabling efficient exploration and optimization. Implemented in TSMC's 65 nm CMOS technology (300 MHz, 0.8 V), X-HEEP achieves a minimal footprint of only 0.15 mm2 and consumes just 29 uW of leakage power. As a demonstrator of the configurability and low overhead of X-HEEP as a host platform, we present a study integrating it with near-memory accelerators targeting early-exit dynamic network applications, achieving up to 7.3 x performance speedup and 3.6 x energy improvement on the resulting heterogeneous system compared to CPU-only execution.

Problem

• Configurable RISC-V platform for ultra-low-power TinyAI edge applications
• Seamless integration of accelerators with varying interface requirements
• Supporting multiple development flows including FPGA and ASIC implementation

Innovation

• Configurable RISC-V platform for ultra-low-power edge
• Extendible Accelerator Interface for seamless integration
• Supports FPGA prototyping and ASIC implementation flows