A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node

2026-08-23

AI Summary

研究提出了一种2nm节点的3D 6T SRAM，通过集成BEOL IGO通门与硅纳米片锁存器等技术，解决了芯片尺寸和性能优化问题。

Abstract

We propose a monolithic-3D (M3D) 6T SRAM at the 2nm node, integrating BEOL IGO pass-gates (PGs) with an all-silicon nanosheet latch, buried power rails (BPRs), and Ru interconnects. TCAD calibrated to a state-of-the-art double-gate IGO transistor with a tri-layer HfO$_2$/ZrO$_2$/HfO$_2$ (HZH) gate stack is combined with virtual fabrication and 3D parasitic extraction to realize the first process-aware layout of this topology. A novel neighbor-cell shared source/drain (S/D) bitline (BL) design enlarges the IGO contact area to mitigate contact resistance and restore PG drive without area penalty. The resulting cell achieves a 25\% footprint reduction vs the high-performance (HP) 122 Si baseline while maintaining robust static noise margin (SNM) over a wide supply voltage range. At the 128$\times$256 subarray-level, it reduces write delay by 42.2\% and EDP by 9.7\% compared to the high-density (HD) 111 Si baseline, owing to reduced cell parasitics and wordline (WL) loading from the smaller footprint.

Problem

• monolithic-3D
• 6T SRAM
• 2nm node
• IGO pass-gates
• footprint reduction

Innovation

• monolithic-3D
• BEOL IGO pass-gates
• shared S/D bitline design
• process-aware layout
• reduced footprint