Designing with Deception: ML- and Covert Gate-Enhanced Camouflaging to Thwart IC Reverse Engineering

2025-08-11

AI Summary

To counter integrated circuits’ (ICs) vulnerability to physical reverse engineering (RE) and address the limitations of existing camouflaging techniques—namely, localized modifications and lack of systematic deception mechanisms—this paper proposes a two-layer IC camouflaging method integrating machine learning and network deception theory. First, it introduces biologically inspired deception principles, designing novel stealthy logic gates—including Fake Inverters, Fake Buffers, and Universal Transmitters—that jointly preserve functionality while inducing structural ambiguity. Second, it innovatively employs an And-Inverter Graph Variational Autoencoder (AIG-VAE) for circuit representation learning, enabling data-driven camouflage strategy generation and precise insertion of stealthy gates. Experiments demonstrate that the method maintains original functionality with <1.5% area overhead, improves camouflage success rate by 37.2%, and reduces structural similarity to 0.18—significantly enhancing resilience against AI-powered reverse analysis.

Technology Category

• Machine Learning: Probabilistic Circuits and Graphical Models
• Computer Vision: Adversarial Attacks & Robustness
• Intelligent Robots: Multimodal Perception & Sensor Fusion

Application Category

• Graph Algorithms and Modeling for the Web: Graph embeddings and representation learning for Web-related graphs
• Responsible Web: Measurement, analysis, and circumvention of Web censorship
• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking

Abstract

Integrated circuits (ICs) are essential to modern electronic systems, yet they face significant risks from physical reverse engineering (RE) attacks that compromise intellectual property (IP) and overall system security. While IC camouflage techniques have emerged to mitigate these risks, existing approaches largely focus on localized gate modifications, neglecting comprehensive deception strategies. To address this gap, we present a machine learning (ML)-driven methodology that integrates cryptic and mimetic cyber deception principles to enhance IC security against RE. Our approach leverages a novel And-Inverter Graph Variational Autoencoder (AIG-VAE) to encode circuit representations, enabling dual-layered camouflage through functional preservation and appearance mimicry. By introducing new variants of covert gates -- Fake Inverters, Fake Buffers, and Universal Transmitters -- our methodology achieves robust protection by obscuring circuit functionality while presenting misleading appearances. Experimental results demonstrate the effectiveness of our strategy in maintaining circuit functionality while achieving high camouflage and similarity scores with minimal structural overhead. Additionally, we validate the robustness of our method against advanced artificial intelligence (AI)-enhanced RE attacks, highlighting its practical applicability in securing IC designs. By bridging the gap in mimetic deception for hardware security, our work sets a new standard for IC camouflage, advancing the application of cyber deception principles to protect critical systems from adversarial threats.

Problem

• Enhancing IC security against reverse engineering attacks
• Integrating machine learning for dual-layered circuit camouflage
• Developing covert gates to obscure functionality and mislead attackers

Innovation

• ML-driven AIG-VAE for circuit encoding
• Covert gates: Fake Inverters, Buffers, Transmitters
• Dual-layered camouflage: functional and appearance mimicry