ICMarks: A Robust Watermarking Framework for Integrated Circuit Physical Design IP Protection

2024-04-29

arXiv.org

AI Summary

Existing physical design watermarking techniques for integrated circuits (ICs) neglect routing congestion and timing constraints, often degrading circuit performance. To address this, this paper proposes a zero-overhead, robust watermarking framework embedded during the placement stage. We innovatively design a region-adaptive watermark unit selection mechanism that identifies optimal embedding locations by jointly analyzing congestion and timing sensitivity. Furthermore, we introduce a two-layer encoding embedding structure and formally model typical attacks—including removal and forgery—to rigorously validate robustness. Evaluated on multiple benchmark circuits of varying scales and optimization objectives, our method achieves zero degradation in both total wirelength and critical-path delay. Crucially, it maintains 100% verifiability of ownership under known attacks, thereby simultaneously ensuring strong IP protection and high-quality physical implementation.

Technology Category

• Computer Vision: Adversarial Attacks & Robustness
• Machine Learning: Adversarial Learning & Robustness
• Planning, Routing, and Scheduling: Routing

Application Category

• Security and Privacy: Data transparency and provenance
• User Modeling, Personalization and Recommendation: Attacks and countermeasures in recommendation systems
• Responsible Web: Measurement, analysis, and circumvention of Web censorship

Abstract

Physical design watermarking on contemporary integrated circuit (IC) layout encodes signatures without considering the dense connections and design constraints, which could lead to performance degradation on the watermarked products. This paper presents ICMarks, a quality-preserving and robust watermarking framework for modern IC physical design. ICMarks embeds unique watermark signatures during the physical design's placement stage, thereby authenticating the IC layout ownership. ICMarks's novelty lies in (i) strategically identifying a region of cells to watermark with minimal impact on the layout performance and (ii) a two-level watermarking framework for augmented robustness toward potential removal and forging attacks. Extensive evaluations on benchmarks of different design objectives and sizes validate that ICMarks incurs no wirelength and timing metrics degradation, while successfully proving ownership. Furthermore, we demonstrate ICMarks is robust against two major watermarking attack categories, namely, watermark removal and forging attacks; even if the adversaries have prior knowledge of the watermarking schemes, the signatures cannot be removed without significantly undermining the layout quality.

Problem

• Develops a robust watermarking framework for IC physical design.
• Embeds watermarks without degrading IC layout performance.
• Ensures watermark robustness against removal and forging attacks.

Innovation

• Embeds watermarks during IC placement stage
• Two-level framework enhances watermark robustness
• Minimizes performance impact on IC layout