Circuit-Aware SAT Solving: Guiding CDCL via Conditional Probabilities

2025-08-06

AI Summary

In circuit satisfiability (CSAT) solving, conventional CNF conversion discards structural and functional circuit information, limiting CDCL solver performance. This paper introduces the first circuit-aware SAT solving framework: it employs graph neural networks (GNNs) to model gate-level conditional probabilities and dynamically guides core CDCL decisions—specifically variable phase selection and clause filtering. To our knowledge, this is the first work to incorporate circuit-level probabilistic modeling into SAT solving, explicitly preserving and leveraging the original circuit topology and logical dependencies. Evaluated on real-world logic equivalence verification benchmarks, our approach achieves up to 10× speedup over state-of-the-art methods. Further integrating probability-guided clause filtering reduces total runtime by an additional 23.5%. This work establishes a novel paradigm for structured SAT solving that bridges circuit semantics with modern conflict-driven search.

Technology Category

• Constraint Satisfaction and Optimization: Satisfiability
• Machine Learning: Probabilistic Circuits and Graphical Models
• Reasoning under Uncertainty: Graphical Models

Application Category

• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs

Abstract

Circuit Satisfiability (CSAT) plays a pivotal role in Electronic Design Automation. The standard workflow for solving CSAT problems converts circuits into Conjunctive Normal Form (CNF) and employs generic SAT solvers powered by Conflict-Driven Clause Learning (CDCL). However, this process inherently discards rich structural and functional information, leading to suboptimal solver performance. To address this limitation, we introduce CASCAD, a novel circuit-aware SAT solving framework that directly leverages circuit-level conditional probabilities computed via Graph Neural Networks (GNNs). By explicitly modeling gate-level conditional probabilities, CASCAD dynamically guides two critical CDCL heuristics -- variable phase selection and clause managementto significantly enhance solver efficiency. Extensive evaluations on challenging real-world Logical Equivalence Checking (LEC) benchmarks demonstrate that CASCAD reduces solving times by up to 10x compared to state-of-the-art CNF-based approaches, achieving an additional 23.5% runtime reduction via our probability-guided clause filtering strategy. Our results underscore the importance of preserving circuit-level structural insights within SAT solvers, providing a robust foundation for future improvements in SAT-solving efficiency and EDA tool design.

Problem

• Enhances CSAT solving by preserving circuit structural information
• Guides CDCL heuristics using circuit-level conditional probabilities
• Improves solver efficiency via probability-guided clause filtering

Innovation

• Uses GNNs for circuit-level probability computation
• Guides CDCL heuristics with gate probabilities
• Reduces solving times via probability-guided filtering