Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL

2026-04-29

AI Summary

This work addresses the lack of systematic and highly reliable pre-silicon verification methodologies for high-performance RISC-V computing chips by proposing and implementing an end-to-end pre-silicon verification closed-loop framework. The framework uniquely integrates industrial-grade UVM functional verification, FPGA-based system-level hardware-software co-verification, and CI/CD automation pipelines, enabling continuous, efficient, and scalable verification on large-scale CPU/FPGA infrastructures. The resulting high-robustness verification infrastructure has already supported strategic European initiatives such as EPI and DARE, significantly enhancing the reliability of RISC-V chip designs and the efficiency of software integration throughout the development lifecycle.

Abstract

The Barcelona Zetascale Lab (BZL) project aims to strengthening Europe's capacity in the design and manufacture of RISC-V based high-performance computing chips. In this context, we present a holistic pre-silicon verification and validation (V&V) methodology targeting highly robust RISC-V chip designs. This paper provides an overview of BZL's V&V approach, which integrates three complementary platforms: (1) a UVM-based verification environment to thoroughly validate RTL functionality; (2) an FPGA-based validation platform that enables system-level pre-silicon hardware-software RTL validation; and (3) a CI/CD flow that continuously automates build, deployment, and tests across these domains. By embedding these platforms into an industrial-grade V&V loop and exploiting large-scale CPU and FPGA hardware infrastructures, the BZL project enables continuous evolution of reliable hardware development and software integration. We believe that the BZL's V&V flow represents a robust and scalable foundation for ensuring the pre-silicon functional correctness and system level validation of RISC-V chip designs, and can serve as a key enabler for strategic initiatives in Europe, such as EPI and DARE, and beyond.

Problem

• RISC-V
• Verification and Validation
• pre-silicon
• hardware-software co-validation
• functional correctness

Innovation

• RISC-V
• Verification and Validation
• UVM
• FPGA prototyping
• CI/CD