CLIP-3D: Closed-Loop Evaluation of Performance and Physical Constraints for 3D ICs

2026-07-14

AI Summary

Early exploration of 3D integrated circuit architectures has been hindered by inaccurate modeling of layout-induced thermal, interconnect, and cache effects, leading to unreliable predictions of actual operating frequency and performance. This work proposes CLIP-3D, a left-shifted design flow that maps architectural configurations to physically aware representations without requiring signoff tools, and jointly optimizes cross-layer macro allocation and floorplanning through a thermal-aware placer. Its key innovation lies in introducing, for the first time, a closed-loop, analytical continuous-frequency model that directly targets actual BIPS (billion instructions per second) in joint optimization, eliminating reliance on manually weighted proxy objectives. By integrating McPAT, CACTI, and a HotSpot-compatible 3D thermal model, CLIP-3D substantially improves performance estimation accuracy and enables efficient architectural-level screening of designs free from thermal or interconnect-induced frequency throttling.

Abstract

3D integration packs more power into a smaller footprint, so a candidate design's actual throughput depends on its layout: which macro sits on which tier, where the hot spot lands, and how cache geometry maps to access cycles. Architectural simulators like gem5 report IPC under idealized timing. They do not produce the per-block power map, the cache cycle counts, or the 3D layout that decide the realized billion-instructions-per-second (BIPS), so early-stage 3D-IC exploration selects designs without accounting for the effects that decide whether they throttle on silicon. We present CLIP-3D, a shift-left flow that exposes 3D layout-driven thermal, wire, and cache effects to early-stage architectural exploration before any sign-off tool is invoked. The first stage lifts an architectural configuration into a physical block representation: McPAT for per-block dynamic and leakage power, CACTI for cache geometry and access cycles, and a HotSpot-compatible 3D stack discretization. The second stage runs an analytical 3D thermal-aware floorplanner over that representation. The floorplanner objective embeds a closed-form sustained-frequency expression derived from the linearity of HotSpot's steady-state operator and the standard CMOS power-frequency decomposition. Cross-tier macro assignment and in-plane placement are co-optimized for the realized BIPS rather than for a half-perimeter wirelength (HPWL)-plus-temperature surrogate with hand-tuned weights.

Problem

• 3D IC
• architectural exploration
• thermal effects
• physical constraints
• performance evaluation

Innovation

• 3D IC
• thermal-aware floorplanning
• closed-loop performance evaluation
• shift-left design
• BIPS optimization