Fault-Free Analog Computing with Imperfect Hardware

2025-07-15

AI Summary

Memristor-based analog in-memory computing suffers from low accuracy and reliability due to device failures and parameter drift; existing redundancy or retraining strategies fail to simultaneously satisfy high precision, fixed-weight deployment, and data privacy requirements. This paper proposes a fault-immune paradigm for indirect matrix representation: the target matrix is decomposed into two tunable submatrices, mapped onto defective hardware, and mathematically reconstructed to bypass faulty cells—eliminating the need for hardware redundancy or model retraining. Integrating adaptive programming with optimization algorithms, our approach achieves >99.999% similarity to the ideal DFT matrix under 39% defect rate, reduces communication bit error rate by 56×, and improves computational density and energy efficiency by 196% and 179%, respectively. To the best of our knowledge, this is the first work to achieve ultra-high-precision analog computation under high defect rates, thereby overcoming yield limitations in memristive hardware.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Analogy
• Humans and AI: Other Foundations of Human Computation & AI

Application Category

• Security and Privacy: Large-scale security measurements
• Economics, Online Markets and Human Computation: Data quality aspects of human-annotated datasets
• Graph Algorithms and Modeling for the Web: Graph embeddings and representation learning for Web-related graphs

Abstract

The growing demand for edge computing and AI drives research into analog in-memory computing using memristors, which overcome data movement bottlenecks by computing directly within memory. However, device failures and variations critically limit analog systems' precision and reliability. Existing fault-tolerance techniques, such as redundancy and retraining, are often inadequate for high-precision applications or scenarios requiring fixed matrices and privacy preservation. Here, we introduce and experimentally demonstrate a fault-free matrix representation where target matrices are decomposed into products of two adjustable sub-matrices programmed onto analog hardware. This indirect, adaptive representation enables mathematical optimization to bypass faulty devices and eliminate differential pairs, significantly enhancing computational density. Our memristor-based system achieved >99.999% cosine similarity for a Discrete Fourier Transform matrix despite 39% device fault rate, a fidelity unattainable with conventional direct representation, which fails with single device faults (0.01% rate). We demonstrated 56-fold bit-error-rate reduction in wireless communication and >196% density with 179% energy efficiency improvements compared to state-of-the-art techniques. This method, validated on memristors, applies broadly to emerging memories and non-electrical computing substrates, showing that device yield is no longer the primary bottleneck in analog computing hardware.

Problem

• Overcoming device failures in analog computing systems
• Enhancing precision and reliability in memristor-based computing
• Eliminating need for redundancy in high-precision applications

Innovation

• Decomposing matrices into adjustable sub-matrices
• Bypassing faulty devices via optimization
• Achieving high fidelity with device faults