Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs

2025-07-09

AI Summary

Pre-layout SRAM simulation suffers from significant post-layout simulation mismatches and costly design iterations due to inaccurate parasitic modeling. To address this, we propose a parasitic-aware pre-layout capacitance prediction method based on a two-stage deep learning framework: (1) a graph neural network (GNN) classifier identifies highly sensitive nodes in the schematic, and (2) a multilayer perceptron (MLP) regressor predicts parasitic capacitances at those nodes. We introduce focal loss to mitigate severe class imbalance in sensitivity classification and explicitly encode hierarchical schematic topology via subcircuit-level graph structural representation. Evaluated on four industrial SRAM designs, our method reduces maximum prediction error by up to 19× and accelerates simulation by up to 598× compared to layout extraction, outperforming state-of-the-art approaches significantly.

Technology Category

• Machine Learning: Probabilistic Circuits and Graphical Models
• Planning, Routing, and Scheduling: Planning/Scheduling and Learning
• Search and Optimization: Learning to Search

Application Category

• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs

Abstract

To achieve higher system energy efficiency, SRAM in SoCs is often customized. The parasitic effects cause notable discrepancies between pre-layout and post-layout circuit simulations, leading to difficulty in converging design parameters and excessive design iterations. Is it possible to well predict the parasitics based on the pre-layout circuit, so as to perform parasitic-aware pre-layout simulation? In this work, we propose a deep-learning-based 2-stage model to accurately predict these parasitics in pre-layout stages. The model combines a Graph Neural Network (GNN) classifier and Multi-Layer Perceptron (MLP) regressors, effectively managing class imbalance of the net parasitics in SRAM circuits. We also employ Focal Loss to mitigate the impact of abundant internal net samples and integrate subcircuit information into the graph to abstract the hierarchical structure of schematics. Experiments on 4 real SRAM designs show that our approach not only surpasses the state-of-the-art model in parasitic prediction by a maximum of 19X reduction of error but also significantly boosts the simulation process by up to 598X speedup.

Problem

• Predict pre-layout parasitic capacitance in SRAM designs
• Reduce discrepancies between pre and post-layout simulations
• Minimize design iterations with accurate parasitic prediction

Innovation

• Deep-learning 2-stage model for parasitic prediction
• Combines GNN classifier and MLP regressors
• Uses Focal Loss to manage class imbalance