Inverter Redistribution through Self-Dual and Self-Anti-Dual Function Transformation

2026-05-09

AI Summary

This work addresses a critical gap in existing AIG-based technology mapping methods, which neglect the distribution of complementary edges (inverters), leading to a discrepancy in delay estimation between technology-independent optimization and technology-dependent mapping—particularly detrimental to critical paths. To bridge this gap, the authors propose a delay-driven preprocessing technique that leverages self-dual and self-anti-dual Boolean function transformations to redistribute complementary edges prior to mapping, thereby optimizing inverter placement along critical paths. This approach represents the first application of such Boolean transformations to complementary edge redistribution, effectively reconciling the modeling disparity of inverters in the synthesis flow. Evaluated on the EPFL combinational benchmark suite, the method achieves an average delay reduction of 0.49%, with up to 3.86% improvement on the sqrt circuit, all while preserving the original logic functionality and timing characteristics.

Abstract

And-Inverter Graph (AIG)-based logic synthesis has been a cornerstone of digital design automation for several decades. While numerous optimization techniques have been developed for both technology-independent and technology-dependent synthesis stages, existing technology mapping approaches predominantly employ graph-covering strategies directly on AIG representations without adequately addressing complemented edge distribution. Neglecting inverters creates a significant disconnect: complemented edges are systematically overlooked in technology-independent cost functions, yet they abruptly become critical during technology-dependent mapping. In this work, we introduce a delay-driven pre-processing stage that operates prior to technology mapping, designed to strategically redistribute complemented edges and mitigate the inverter-induced costs on critical paths. Experimental validation demonstrates that our delay-targeted methodology not only preserves original delay characteristics but also enables performance improvements. Notably, arithmetic logic in the EPFL combinational benchmark exhibits particular sensitivity to this approach, with our method achieving an average delay reduction of 0.49% and a maximum improvement of 3.86% on the case sqrt.

Problem

• inverter redistribution
• complemented edge
• technology mapping
• logic synthesis
• critical path delay

Innovation

• Inverter Redistribution
• Self-Dual Function
• Self-Anti-Dual Function
• Delay-Driven Optimization
• And-Inverter Graph