CnC-PRAC: Coalesce, not Cache, Per Row Activation Counts for an Efficient in-DRAM Rowhammer Mitigation

2025-06-13

AI Summary

Existing PRAC (Per-Row Activation Count) Rowhammer mitigation schemes for DDR5 and future DRAM suffer from high performance overhead (up to 10%), while alternatives like Chronus incur excessive dynamic energy consumption. Method: This paper proposes a cacheless PRAC implementation that fully decouples counting operations from the critical data-access path via memory access reordering and intra-row count-access merging. It introduces a novel “merge-not-cache” design paradigm, leveraging request buffering, read-modify-write merging, and physical row-level memory access aggregation. Contribution/Results: Compared to Chronus, the proposed scheme reduces row activations by 75–83%, incurs negligible performance degradation, and increases dynamic energy consumption by only 0.84–1.0%. It achieves an optimal trade-off among security, performance, and energy efficiency—enabling practical, low-overhead PRAC deployment in next-generation DRAM systems.

Technology Category

• Machine Learning: Hardware-aware ML
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Search and Optimization: Distributed Search

Application Category

• Security and Privacy: Large-scale security measurements
• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking
• Responsible Web: Data and user privacy-enhancing technologies for the Web

Abstract

JEDEC has introduced the Per Row Activation Counting (PRAC) framework for DDR5 and future DRAMs to enable precise counting of DRAM row activations using per-row activation counts. While recent PRAC implementations enable holistic mitigation of Rowhammer attacks, they impose slowdowns of up to 10% due to the increased DRAM timings for performing a read-modify-write of the counter. Alternatively, recent work, Chronus, addresses these slowdowns, but incurs energy overheads due to the additional DRAM activations for counters. In this paper, we propose CnC-PRAC, a PRAC implementation that addresses both performance and energy overheads. Unlike prior works focusing on caching activation counts to reduce their overheads, our key idea is to reorder and coalesce accesses to activation counts located in the same physical row. Our design achieves this by decoupling counter access from the critical path of data accesses. This enables optimizations such as buffering counter read-modify-write requests and coalescing requests to the same row. Together, these enable a reduction in row activations for counter accesses by almost 75%-83% compared to state-of-the-art solutions like Chronus and enable a PRAC implementation with negligible slowdown and a minimal dynamic energy overhead of 0.84%-1% compared to insecure DDR5 DRAM.

Problem

• Reduces DRAM slowdowns from Rowhammer mitigation
• Minimizes energy overheads in activation counting
• Optimizes counter access by coalescing row requests

Innovation

• Coalesces activation counts per DRAM row
• Decouples counter access from data path
• Reduces row activations by 75%-83%