VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification

2025-05-16

AI Summary

This work addresses the end-to-end generation of formally verifiable Verilog code from high-level hardware specifications—a longstanding challenge in hardware design automation, where conventional approaches lack formal correctness guarantees. We propose the first formality-aware evaluation benchmark for Verilog code generation; construct the first multi-level, reasoning-driven dataset tailored for hardware code synthesis, along with a lightweight model family; and integrate large language model–based reasoning with formal verification techniques—including combinational equivalence checking, model checking, Verilog syntactic constraint modeling, and domain-specific fine-tuning. Our approach achieves 100% formal verification pass rates across multiple representative hardware modules, while significantly improving functional correctness and synthesis feasibility. The open-sourced dataset and models have been widely adopted by the hardware design and formal methods communities.

Technology Category

• Machine Learning: Hardware-aware ML
• Natural Language Processing: Code Generation / Program Synthesis from Natural Language
• Knowledge Representation and Reasoning: Automated Reasoning and Theorem Proving

Application Category

• Economics, Online Markets and Human Computation: Data quality aspects of human-annotated datasets
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics

Abstract

This paper introduces VeriThoughts, a novel dataset designed for reasoning-based Verilog code generation. We establish a new benchmark framework grounded in formal verification methods to evaluate the quality and correctness of generated hardware descriptions. Additionally, we present a suite of specialized small-scale models optimized specifically for Verilog generation. Our work addresses the growing need for automated hardware design tools that can produce verifiably correct implementations from high-level specifications, potentially accelerating the hardware development process while maintaining rigorous correctness guarantees. Our code and data are available at href{https://github.com/wilyub/VeriThoughts}{this URL}.

Problem

• Automated Verilog code generation using reasoning techniques
• Formal verification for hardware description correctness
• Specialized models for efficient Verilog generation

Innovation

• Novel dataset for reasoning-based Verilog generation
• Benchmark framework using formal verification methods
• Specialized small-scale models for Verilog optimization