AIA: A 16nm Multicore SoC for Approximate Inference Acceleration Exploiting Non-normalized Knuth-Yao Sampling and Inter-Core Register Sharing

2026-06-14

AI Summary

This work addresses the computational intensity and limited parallelism of Markov Chain Monte Carlo (MCMC) algorithms in probabilistic graphical model inference, which lead to poor efficiency on general-purpose processors. To overcome these challenges, the authors propose a 16-core RISC-V multicore SoC tailored for edge deployment, featuring an unnormalized Knuth-Yao sampler, an inter-core register-direct communication architecture, and a dedicated interpolation unit, complemented by a custom compiler for efficient task mapping. Fabricated in 16nm CMOS with a 2D mesh topology, the chip achieves a throughput of 1277 MSamples/s at 0.9V and an energy efficiency of 20 GSamples/s/W at 0.7V. These results represent a 2× speedup and 1.45× higher energy efficiency compared to the state-of-the-art MRF accelerator, substantially enhancing both the parallel efficiency and generality of MCMC inference.

Abstract

Probabilistic graphical models (PMs) are popular to empower machine learning with the ability of reasoning and decision-making. To perform approximate inference in PMs, sampling-based Markov Chain Monte Carlo (MCMC) algorithms are commonly employed. Unfortunately, MCMC is compute-intensive and hard to run in parallel, resulting in inefficient execution on modern CPU/GPU platforms. This paper proposes \name{}, an Approximate Inference Accelerator designed to empower decision-making and reasoning at the edge. \name{} consists of a RISC-V host, and a 2D mesh of 16 customized RISC-V cores optimized to efficiently support PM inference, each featuring (i) a novel non-normalized Knuth-Yao sampler and interpolation unit; and (ii) core-to-core direct data access via the register file, which provides solutions for compute-intensive operations. To fully exploit the parallel potential of Markov Chain Monte Carlo (MCMC) algorithms, a customized compiler chain has been developed for effective spatial mapping and scheduling on the chip. \name{} can generate 1277 MSample/s at 0.9V and 20 GSamples/s/W at 0.7V which is up to 2$\times$ faster and 1.45x more energy efficient compared to the previous state-of-the-art Markov Random Field (MRF) accelerator. We further map Bayesian Networks benchmark onto \name{} to show the flexibility of our design.

Problem

• Probabilistic Graphical Models
• Approximate Inference
• Markov Chain Monte Carlo
• Edge Computing
• Sampling Algorithms

Innovation

• Approximate Inference
• Non-normalized Knuth-Yao Sampling
• Inter-Core Register Sharing
• MCMC Acceleration
• RISC-V Multicore SoC