AIA: A Customized Multi-core RISC-V SoC for Discrete Sampling Workloads in 16 nm

2026-06-14

AI Summary

This work addresses the high computational overhead and poor parallel efficiency of sampling-based Markov Chain Monte Carlo (MCMC) inference on conventional CPUs and GPUs, which hinder real-time probabilistic reasoning on edge devices. To overcome these limitations, the authors design and implement AIA, a multicore RISC-V system-on-chip tailored for discrete sampling tasks, fabricated in Intel’s 16nm process. AIA integrates one host core and sixteen customized RISC-V cores arranged in a 2D mesh, featuring dedicated instructions and datapaths for unnormalized Knuth–Yao sampling, a nonlinear function interpolation unit, and direct register-file interconnects between neighboring cores to minimize data movement. A co-designed compiler toolchain optimizes spatial mapping and scheduling of MCMC algorithms. Experimental results demonstrate that the proposed architecture substantially improves energy efficiency and execution speed of MCMC inference at the edge, enabling hardware-supported real-time decision-making in safety-critical applications.

Abstract

Probabilistic models (PMs) are essential in advancing machine learning capabilities, particularly in safety-critical applications involving reasoning and decision-making. Among the methods employed for inference in these models, sampling-based Markov Chain Monte Carlo (MCMC) techniques are widely used. However, MCMC methods come with significant computational costs and are inherently challenging to parallelize, resulting in inefficient execution on conventional CPU/GPU platforms. To overcome these challenges, this paper presents AIA, a multi-core RISC-V System-on-Chip (SoC) design fabricated using Intel's 16 nm process technology. Our Approximate Inference Accelerator (AIA) is specifically designed to empower edge devices with robust decision-making and reasoning abilities. The AIA architecture incorporates a RISC-V host processor to manage chip-to-chip data communication and a 2D mesh of 16 custom versatile RISC-V cores optimized for high-efficiency approximate inference. Each core features (i) custom instructions and datapath blocks for non-normalized Knuth-Yao (KY) sampling, as well as for the interpolation of non-linear functions (e.g., logarithmic, exponential), and (ii) direct data access to the register file of each neighboring core, to reduce the data movement costs of frequent data exchanges between nearby cores. To further capitalize on the parallelism potential in MCMC algorithms, we developed a specialized compile chain that enables efficient spatial mapping and scheduling across the cores.

Problem

• Markov Chain Monte Carlo
• probabilistic models
• approximate inference
• sampling-based inference
• computational efficiency

Innovation

• RISC-V SoC
• Markov Chain Monte Carlo (MCMC)
• Approximate Inference
• Custom Instructions
• Inter-core Communication