🤖 AI Summary
This work addresses the high latency in neutral-atom quantum computing imposed by classical processing tasks such as fluorescence imaging and atom rearrangement. The authors propose an end-to-end control architecture based on a Zynq UltraScale+ FPGA, which for the first time tightly integrates a custom image-processing module and a novel rearrangement algorithm on a single chip. By leveraging hardware-level pipelining, the system enables streaming instruction generation and eliminates round-trip delays caused by host-mediated communication. Evaluated on a 16×16 atomic array, the architecture achieves an end-to-end latency of 25.3 ms, a time-to-first-action of 4 ms, and an average action-generation interval of 1 ms, substantially enhancing real-time performance while demonstrating strong scalability.
📝 Abstract
Neutral Atom Quantum Computing (NAQC) is an emerging modality for scalable quantum computation, valued for its long coherence times and the naturally identical atomic qubits. However, one of the main drawbacks is its slow execution rate, dominated by lengthy classical processing tasks, such as fluorescence imaging, cooling, and atom rearrangement. We address this bottleneck with AtomFlow, a field-programmable gate array (FPGA)-based control architecture that consolidates fluorescence-image analysis and a newly developed atom-rearrangement algorithm onto a single Zynq UltraScale+ device. By co-locating the two stages on the same board and emitting rearrangement moves in a streaming fashion as soon as they are computed, AtomFlow eliminates the round-trip latency of conventional host-mediated pipelines. Evaluated on a 16x16 atom array, AtomFlow achieves an end-to-end latency of 25.3 ms with a first-move latency of 4 ms and an average move generation of 1 ms. Furthermore, our scalability analysis demonstrates that the architecture can readily support larger atom arrays within a single-board resource budget.