ARMOR-IMC: Adaptive Resource Mapping for Operational Robustness via Secure In-Memory Computing

2026-07-12

AI Summary

This work addresses the dual challenges of reliability degradation due to process variations and vulnerability to power side-channel attacks in analog in-memory computing (IMC) systems, which existing approaches struggle to mitigate jointly. The paper presents the first post-training, co-design defense framework tailored for SOT-MTJ-based analog IMC accelerators, eliminating the need for model retraining. The framework introduces a Variation Impact Score (VIS) to guide fault-tolerant resource mapping, effectively mitigating the adverse effects of process-induced deviations, and employs a Leakage-per-Inference (LPI) metric to quantify and suppress side-channel information leakage. Experimental results using IMAC-Sim demonstrate that, even when process variations degrade inference accuracy by over 50%, the proposed method restores accuracy close to the original baseline while substantially reducing the effectiveness of correlation-based power analysis attacks.

Abstract

The massive data-movement overhead in traditional architectures has led to the adoption of In-Memory Computing (IMC) for energy-efficient Deep Neural Network (DNN) processing. By leveraging emerging devices like Spin-Orbit Torque Magnetic Tunnel Junctions (SOT-MTJs), IMC bypasses the "memory wall" and reduces leakage power inherent in traditional CMOS. However, this shift introduces dual hardware threats: manufacturing Process Variation (PV) degrades reliability and increases vulnerability to fault injection, while power Side-Channel Attacks (SCAs) compromise security. Existing defenses address these threats in isolation. This work presents a posttraining framework that simultaneously hardens analog IMC accelerators against both threats without retraining the model. Implemented in the IMAC-Sim simulator, our approach uses the proposed Variation Impact Score (VIS) to guide the mapping of Fault Observation Windows (FOWs) and introduces the Leakage Per Inference (LPI) metric to quantify input-dependent power variability under stochastic injection and the resulting reduction in effective signal-to-noise ratio. Experiments show that PV-induced faults can degrade accuracy by over 50%, while our method restores near-baseline accuracy and mitigates the threat of correlation-based power analysis attacks.

Problem

• Process Variation
• Side-Channel Attacks
• In-Memory Computing
• Fault Injection
• Hardware Security

Innovation

• In-Memory Computing
• Process Variation
• Side-Channel Attacks
• Adaptive Resource Mapping
• Fault Tolerance