๐ค AI Summary
Existing automated macro placement methods inadequately model data flowโparticularly overlooking implicit inter-cluster data dependencies between macros and standard-cell clusters.
Method: This work introduces, for the first time, a cross-granularity data-flow modeling framework that explicitly captures and converts such implicit data flows into optimizable placement constraints. It further proposes a congestion-aware macro area-balancing optimization mechanism and a direction-sensitive, data-flow-driven macro flipping algorithm.
Results: Evaluated on mainstream benchmarks, the method achieves an average 7.9% reduction in half-perimeter wirelength (HPWL), an 82.5% decrease in congestion overflow, and improvements of 36.97% and 59.44% in worst negative slack (WNS) and total negative slack (TNS), respectively, with negligible runtime overhead (<1.5%). This work presents the first systematic solution for intelligent chip placement that jointly incorporates fine-grained data-flow semantics and physical implementation constraints.
๐ Abstract
Dataflow is a critical yet underexplored factor in automatic macro placement, which is becoming increasingly important for developing intelligent design automation techniques that minimize reliance on manual adjustments and reduce design iterations. Existing macro or mixed-size placers with dataflow awareness primarily focus on intrinsic relationships among macros, overlooking the crucial influence of standard cell clusters on macro placement. To address this, we propose DAS-MP, which extracts hidden connections between macros and standard cells and incorporates a series of algorithms to enhance dataflow awareness, integrating them into placement constraints for improved macro placement. To further optimize placement results, we introduce two fine-tuning steps: (1) congestion optimization by taking macro area into consideration, and (2) flipping decisions to determine the optimal macro orientation based on the extracted dataflow information. By integrating enhanced dataflow awareness into placement constraints and applying these fine-tuning steps, the proposed approach achieves an average 7.9% improvement in half-perimeter wirelength (HPWL) across multiple widely used benchmark designs compared to a state-of-the-art dataflow-aware macro placer. Additionally, it significantly improves congestion, reducing overflow by an average of 82.5%, and achieves improvements of 36.97% in Worst Negative Slack (WNS) and 59.44% in Total Negative Slack (TNS). The approach also maintains efficient runtime throughout the entire placement process, incurring less than a 1.5% runtime overhead. These results show that the proposed dataflow-driven methodology, combined with the fine-tuning steps, provides an effective foundation for macro placement and can be seamlessly integrated into existing design flows to enhance placement quality.