LocalV: Exploiting Information Locality for IP-level Verilog Generation

2026-01-31

AI Summary

This work addresses three key challenges in industrial-scale IP module RTL code generation: difficulty in understanding long design documents, declining correctness in long-code generation, and complex debugging. To tackle these issues, the authors propose LocalV, a multi-agent framework that introduces a divide-and-conquer strategy grounded in the locality of hardware design information. By hierarchically partitioning documentation, enforcing interface-consistent merging, and employing an AST-guided, locality-aware debugging mechanism, LocalV decomposes long-horizon generation tasks into scalable short-document-to-short-code subtasks. Evaluated on the RealBench benchmark, LocalV achieves a 45.0% functional pass rate, substantially outperforming the current state-of-the-art method at 21.6%, thereby demonstrating its effectiveness and superiority in automated Verilog code generation and debugging.

Technology Category

• Natural Language Processing: Code Generation / Program Synthesis from Natural Language
• Search and Optimization: Local Search
• Machine Learning: Hardware-aware ML

Application Category

• Responsible Web: Machine-in-the-loop, human agency and autonomy
• Search and Retrieval-Augmented AI: Vertical and domain-specific search
• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems

Abstract

The generation of Register-Transfer Level (RTL) code is a crucial yet labor-intensive step in digital hardware design, traditionally requiring engineers to manually translate complex specifications into thousands of lines of synthesizable Hardware Description Language (HDL) code. While Large Language Models (LLMs) have shown promise in automating this process, existing approaches-including fine-tuned domain-specific models and advanced agent-based systems-struggle to scale to industrial IP-level design tasks. We identify three key challenges: (1) handling long, highly detailed documents, where critical interface constraints become buried in unrelated submodule descriptions; (2) generating long RTL code, where both syntactic and semantic correctness degrade sharply with increasing output length; and (3) navigating the complex debugging cycles required for functional verification through simulation and waveform analysis. To overcome these challenges, we propose LocalV, a multi-agent framework that leverages information locality in modular hardware design. LocalV decomposes the long-document to long-code generation problem into a set of short-document, short-code tasks, enabling scalable generation and debugging. Specifically, LocalV integrates hierarchical document partitioning, task planning, localized code generation, interface-consistent merging, and AST-guided locality-aware debugging. Experiments on RealBench, an IP-level Verilog generation benchmark, demonstrate that LocalV substantially outperforms state-of-the-art (SOTA) LLMs and agents, achieving a pass rate of 45.0% compared to 21.6%.

Problem

• RTL generation
• IP-level design
• information locality
• Verilog
• hardware description

Innovation

• information locality
• multi-agent framework
• IP-level Verilog generation
• hierarchical document partitioning
• AST-guided debugging