Simulation-Aware In-Context Policy Improvement for LLM-Aided Analog Layout Refinement

2026-08-13

AI Summary

This study addresses the challenges of expensive simulations and low sample efficiency in analog IC layout optimization by proposing a simulation-aware large language model (LLM) multi-agent framework. The method introduces compact layout representations and context-aware policy refinement mechanisms, enabling efficient parameter tuning through an iterative execute-observe-reflect loop. Validated on real-world circuits, the approach significantly outperforms traditional heuristic and Bayesian optimization methods with only tens of simulations, substantially improving post-layout performance. By effectively overcoming the limitations of existing techniques regarding geometric context awareness and optimization inefficiency, this work establishes a novel paradigm for intelligent analog electronic design automation.

Abstract

Analog IC layout design remains a labor-intensive iterative process dominated by simulation-driven refinement. Although end-to-end layout generators accelerate initial placement and routing, they still require experts to manually tune layout optimization parameters with repeated post-layout simulations for stringent design specifications. While Bayesian Optimization (BO) is widely adopted for parameter tuning in analog IC design, at the layout level it typically requires hundreds to thousands of evaluations, each involving costly parasitic extraction and post-layout simulation, which makes it impractical. Recently, Large Language Models (LLMs) have demonstrated potential in improving the sample efficiency of such simulation-driven tuning. However, their restricted access to geometric layout context and design-specific heuristics limits their ability to manipulate the layout optimization process. In this paper, we propose a simulation-aware LLM multi-agent framework that performs in-context policy improvement (ICPI) by iteratively updating layout optimization parameters exposed by an analog layout generator through an act-observe-reflect loop on compact structured layout representations. Experiments on real-world analog circuits show that, with only tens of post-layout simulations, our approach improves post-layout performance over the generator's built-in heuristics and BO-based tuning method.

Problem

• Analog IC layout refinement
• Simulation-driven tuning
• Large Language Models
• Sample efficiency
• Layout optimization

Innovation

• Simulation-Aware LLM
• In-Context Policy Improvement
• Multi-Agent Framework
• Analog Layout Refinement
• Structured Layout Representation