Concept of a System-on-Chip Research Platform Benchmarking Interaction of Memristor-based Bio-inspired Computing Paradigms

2025-05-16

AI Summary

To address poor post-fabrication compatibility and the lack of unified hardware infrastructure for cross-paradigm evaluation in memristor-CMOS heterogeneous integration, this paper designs and implements a reconfigurable SoC research platform tailored for neuromorphic computing. The platform introduces, for the first time, a benchmark architecture specifically optimized for post-CMOS integration of memristors, incorporating heterogeneous memristor arrays, a programmable network-on-chip (NoC), high-speed on-chip and chip-to-chip interfaces, and a high-bandwidth real-time monitoring module. Leveraging hardware-software co-design, it enables dynamic co-execution and interactive evaluation of diverse biologically inspired computing paradigms—including spiking neural networks and in-memory computing. Experimental results demonstrate significant advantages in throughput, measurement flexibility, and scalability. This work establishes the first open-source, extensible hardware benchmark for standardized evaluation of memristor-based neuromorphic chips.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Humans and AI: Other Foundations of Human Computation & AI

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Economics, Online Markets and Human Computation: Economics and fairness of platforms and recommendation systems
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics

Abstract

A system architecture is suggested for a System on Chip that will combine several different memristor-based, bio-inspired computation arrays with inter- and intra-chip communication. It will serve as a benchmark system for future developments. The architecture takes the special requirements into account which are caused by the memristor co-integration on commercial CMOS structures in a post processing step of the chip. The interface considers the necessary data bandwidth to monitor the internal Network on Chip at speed and provides enough flexibility to give different measurement options.

Problem

• Benchmarking memristor-based bio-inspired computing paradigms
• Integrating memristors with commercial CMOS structures
• Ensuring high-speed data bandwidth for Network on Chip

Innovation

• Combines memristor-based bio-inspired computation arrays
• Integrates memristor with commercial CMOS structures
• Provides flexible high-speed NoC monitoring interface