NeuroSim V1.5: Improved Software Backbone for Benchmarking Compute-in-Memory Accelerators with Device and Circuit-level Non-idealities

2025-05-05

AI Summary

To address the energy-efficiency and latency bottlenecks in AI computing arising from data movement in von Neumann architectures, this paper proposes a high-fidelity co-simulation framework tailored for analog compute-in-memory (ACIM) accelerators. Methodologically, it achieves the first seamless integration with TensorRT’s quantization pipeline; introduces a flexible noise injection mechanism based on pre-characterized statistical models; and supports behavioral-level abstraction of emerging non-volatile devices (e.g., capacitive cells), incorporating SPICE- and silicon-measurement-driven modeling of hardware non-idealities. The framework delivers a 6.5× speedup in simulation throughput, enables accuracy–energy joint optimization across diverse neural networks—including CNNs and Transformers—and facilitates systematic exploration of critical design parameters. Crucially, it maintains model accuracy while substantially improving hardware efficiency.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Search and Optimization: Sampling/Simulation-based Search

Application Category

• User Modeling, Personalization and Recommendation: User modeling and simulation for interactive and conversational systems
• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs

Abstract

The exponential growth of artificial intelligence (AI) applications has exposed the inefficiency of conventional von Neumann architectures, where frequent data transfers between compute units and memory create significant energy and latency bottlenecks. Analog Computing-in-Memory (ACIM) addresses this challenge by performing multiply-accumulate (MAC) operations directly in the memory arrays, substantially reducing data movement. However, designing robust ACIM accelerators requires accurate modeling of device- and circuit-level non-idealities. In this work, we present NeuroSim V1.5, introducing several key advances: (1) seamless integration with TensorRT's post-training quantization flow enabling support for more neural networks including transformers, (2) a flexible noise injection methodology built on pre-characterized statistical models, making it straightforward to incorporate data from SPICE simulations or silicon measurements, (3) expanded device support including emerging non-volatile capacitive memories, and (4) up to 6.5x faster runtime than NeuroSim V1.4 through optimized behavioral simulation. The combination of these capabilities uniquely enables systematic design space exploration across both accuracy and hardware efficiency metrics. Through multiple case studies, we demonstrate optimization of critical design parameters while maintaining network accuracy. By bridging high-fidelity noise modeling with efficient simulation, NeuroSim V1.5 advances the design and validation of next-generation ACIM accelerators. All NeuroSim versions are available open-source at https://github.com/neurosim/NeuroSim.

Problem

• Modeling device and circuit non-idealities in ACIM accelerators
• Integrating noise injection for accurate neural network simulation
• Enhancing simulation speed and device support for design exploration

Innovation

• Integration with TensorRT for neural networks
• Flexible noise injection using statistical models
• Support for emerging non-volatile capacitive memories